Integrated circuits and methods for operating integrated circuits with non-volatile memory

1. An integrated circuit comprising:

a semiconductor substrate doped with a first conductivity-determining impurity and having formed therein:

a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity;

a second well, formed within the first well, and doped with the first conductivity-determining impurity; and

a third well spaced apart from the first and second wells and doped with the second conductivity-determining impurity;

a floating gate structure formed over the semiconductor substrate and comprising:

a first gate element disposed over the second well and being separated from the second well with a dielectric layer;

a second gate element disposed over the third well and being separated from the third well with the dielectric layer; and

a conductive connector that electrically connects the first and second gate elements;

source and drain regions disposed in the second well and doped with the second conductivity-determining impurity, the source and drains regions having conductive contacts formed thereto, wherein the second well, the first gate element, the source and drain regions, and the dielectric layer form a transistor structure;

a first terminal formed of electrical contacts to the first and second wells; and

a second terminal formed of electrical contacts to the third well.

2. The integrated circuit of claim 1 , wherein the first conductivity-determining impurity is of the p-type and the second-conductivity determining impurity is of the n-type.

3. The integrated circuit of claim 1 , wherein the second well comprises a region heavily-doped with the first conductivity-determining impurity with which the electrical contact to the second well is connected.

4. The integrated circuit of claim 1 , wherein the first well comprises a region heavily-doped with the second conductivity-determining impurity with which the electrical contract to the first well is connected.

5. The integrated circuit of claim 1 , wherein the third well comprises a plurality of heavily-doped regions.

6. The integrated circuit of claim 5 , wherein at least one region of the plurality of heavily-doped regions comprises the conductivity-determining impurity of the first type.

7. The integrated circuit of claim 6 , wherein at least one region of the plurality of heavily-doped regions comprises the conductivity-determining impurity of the second type, and wherein the heavily-doped regions of the first and second types are provided in alternative order within the third well.

8. The integrated circuit of claim 1 , wherein a surface area of the first gate element is smaller than a surface area of the second gate element.

9. The integrated circuit of claim 8 , wherein the second gate element comprises a three-pronged configuration.

10. The integrated circuit of claim 1 , wherein the first and second gate elements comprise a polycrystalline silicon material.

11. The integrated circuit of claim 1 , wherein the dielectric layer comprises a silicon oxide material having a thickness of about 40 Angstroms to about 150 Angstroms.

12. The integrated circuit of claim 1 , wherein the semiconductor substrate is a bulk silicon substrate.

13. The integrated circuit of claim 1 , wherein the second well, the dielectric layer, and the first gate element form a tunneling capacitor.

14. The integrated circuit of claim 13 , wherein the third well, the dielectric layer, and the second gate element form a control capacitor.

15. The integrated circuit of claim 14 , wherein the control capacitor has a higher capacitance than the tunneling capacitor.

16. The integrated circuit of claim 15 , wherein the control capacitor is in electrical communication with the tunneling capacitor.

17. A method of operating an integrated circuit, wherein the integrated circuit is defined as comprising the following structures:

a semiconductor substrate doped with a first conductivity-determining impurity and having formed therein:

a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity;

a second well, formed within the first well, and doped with the first conductivity-determining impurity; and

a third well spaced apart from the first and second wells and doped with the second conductivity-determining impurity;

a floating gate structure formed over the semiconductor substrate and comprising:

a first gate element disposed over the second well and being separated from the second well with a dielectric layer;

a second gate element disposed over the third well and being separated from the third well with the dielectric layer; and

a conductive connector that electrically connects the first and second gate elements;

source and drain regions disposed in the second well and doped with the second conductivity-determining impurity, the source and drains regions having conductive contacts formed thereto;

a first terminal formed of electrical contacts to the first and second wells; and

a second terminal formed of electrical contacts to the third well, the method comprising the steps of:

selecting one of a write procedure, an erase procedure, and a read procedure;

if the write procedure is selected, applying a voltage from about 15 volts to about 30 volts to the second terminal;

if the erase procedure is selected, applying a voltage from about 15 volts to about 30 volts to the first terminal; and

if the read procedure is selected:

applying a voltage from about 1 volt to about 5 volts to the drain; and

determining whether a current is conducted between the source and the drain.

18. An integrated circuit comprising:

a semiconductor substrate doped with a first conductivity-determining impurity and having formed therein:

a first well that is defined as a first area of the substrate doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity;

a second well, formed within the first well, and that is defined as a second area of the substrate doped with the first conductivity-determining impurity; and

a third well spaced apart from the first and second wells and that is defined as a third area of the substrate doped with the second conductivity-determining impurity;

a floating gate structure formed over the semiconductor substrate and comprising:

a first gate element disposed over the second well and being separated from the second well with a dielectric layer;

a second gate element disposed over the third well and being separated from the third well with the dielectric layer; and

a conductive connector that electrically connects the first and second gate elements;

source and drain regions disposed in the second well and doped with the second conductivity-determining impurity, the source and drains regions having conductive contacts formed thereto, wherein the second well, the first gate element, the source and drain regions, and the dielectric layer form a transistor structure, and wherein an area underneath the first gate element and between the source and drain regions defines a channel region of the transistor structure through which an electrical current can flow;

a first terminal formed of electrical contacts to the first and second wells; and

a second terminal formed of electrical contacts to the third well.