Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells
Some embodiments include methods of forming vertically-stacked memory cells. An opening is formed to extend partially through a stack of alternating electrically insulative levels and electrically conductive levels. A liner is formed along sidewalls of the opening, and then the stack is etched to extend the opening. The liner is at least partially consumed during the etch and forms passivation material. Three zones occur during the etch, with one of the zones being an upper zone of the opening protected by the liner, another of the zones being an intermediate zone of the opening protected by passivation material but not the liner, and another of the zones being a lower zone of the opening which is not protected by either passivation material or the liner. Cavities are formed to extend into the electrically conductive levels along sidewalls of the opening. Charge blocking dielectric and charge-storage structures are formed within the cavities.
1. A method of fabricating integrated structures, comprising:
forming an opening to extend partially through a stack of alternating first and second levels;
forming a liner along sidewalls of the opening;
extending the opening into the stack utilizing etching conditions that penetrate the first and second levels and that remove at least a majority of the liner; and
wherein the first and second levels comprise silicon dioxide and conductively-doped silicon, respectively; and wherein the liner comprises one or more of tungsten silicide, titanium nitride, silicon nitride, carbon, polycrystalline silicon and oxide having a higher dielectric constant than silicon dioxide.
2. The method of claim 1 wherein the second levels comprise conductively-doped polysilicon.
3. A method of fabricating integrated structures, comprising:
forming an opening to extend partially through a stack of alternating first and second levels;
forming a liner along sidewalls of the opening;
extending the opening into the stack utilizing etching conditions that penetrate the first and second levels and that remove at least a majority of the liner; and
wherein the first and second levels comprise silicon dioxide and conductively-doped silicon, respectively; wherein the liner comprises silicon nitride; and wherein the etching conditions utilize one or more of HBr, CH 2 F 2 , CH 4 , C 2 H 2 , H 2 , NF 3 , C 4 F 8 , C 4 F 6 , O 2 , Ar, CHF 3 , CH 3 F, BCl 3 and SF 6 .
4. A method of fabricating integrated structures, comprising:
forming an opening to extend partially through a stack of alternating first and second levels;
forming a liner along sidewalls of the opening;
extending the opening into the stack utilizing etching conditions that penetrate the first and second levels and that remove at least a majority of the liner; and
wherein the first and second levels comprise silicon dioxide and conductively-doped polysilicon, respectively; wherein the liner comprises silicon nitride; and wherein the etching conditions utilize one or more of HBr, CH 2 F 2 , CH 4 , C 2 H 2 , H 2 , NF 3 , C 4 F 8 , C 4 F 6 , O 2 , Ar, CHF 3 , CH 3 F, BCl 3 and SF 6 .
5. A method of fabricating integrated structures, comprising:
forming an opening to extend partially through a stack of alternating first and second levels;
forming a liner along sidewalls of the opening; the liner having a thickness within a range of from greater than 0 nanometers to about 20 nanometers;
while the liner is along the sidewalls, extending the opening into the stack; and
wherein liner is at least partially consumed during the etch.
6. A method of fabricating integrated structures, comprising:
forming an opening to extend partially through a stack of alternating first and second levels;
forming a liner along sidewalls of the opening; the liner having a thickness within a range of from greater than 0 nanometers to about 20 nanometers;
while the liner is along the sidewalls, extending the opening into the stack; and
wherein the first and second levels are electrically insulative and electrically conductive, respectively.
7. A method of fabricating integrated structures, comprising:
forming an opening to extend partially through a stack of alternating first and second levels;
forming a liner along sidewalls of the opening; the liner having a thickness within a range of from greater than 0 nanometers to about 20 nanometers;
while the liner is along the sidewalls, extending the opening into the stack; and
wherein the first and second levels comprise silicon dioxide and conductively-doped silicon, respectively.
8. The method of claim 7 wherein the liner comprises electrically conductive material.
9. The method of claim 8 wherein the liner comprises one or both of tungsten silicide and titanium nitride.
10. The method of claim 7 wherein the liner comprises one or more of silicon nitride, carbon and polycrystalline silicon, respectively.
11. The method of claim 7 wherein the liner comprises an oxide having a dielectric constant greater than that of silicon dioxide.
12. The method of claim 7 wherein the liner comprises one or more of aluminum oxide, hafnium oxide, zirconium oxide, hafnium silicate and zirconium silicate.
13. A method of fabricating integrated structures, comprising:
forming an opening to extend partially through a stack of alternating first and second levels;
forming a liner along sidewalls of the opening; the liner having a thickness within a range of from greater than 0 nanometers to about 20 nanometers;
while the liner is along the sidewalls, extending the opening into the stack; and
wherein the first and second levels comprise silicon nitride and conductively-doped silicon, respectively.
14. A method of fabricating integrated structures, comprising:
forming a first opening to extend partially through a stack of alternating electrically conductive levels and electrically insulative levels;
forming a liner along sidewalls of the first opening; the liner having a thickness within a range of from greater than 0 nanometers to about 20 nanometers; and
extending the opening into the stack with an etch to form a second opening; the liner being at least partially consumed during the etch and forming passivation material which protects sidewalls of a region of the second opening beneath the liner.
15. The method of claim 14 wherein the liner is entirely consumed during the etch.
16. The method of claim 14 wherein the liner is only partially consumed during the etch.
17. The method of claim 14 wherein the liner comprises one or more of silicon nitride, carbon, titanium nitride, tungsten silicide and polycrystalline silicon, respectively.
18. The method of claim 14 wherein the liner comprises silicon nitride over polycrystalline silicon; and wherein the silicon nitride is entirely consumed during the etch.
19. The method of claim 14 wherein the electrically conductive levels and electrically insulative levels comprise conductively-doped silicon and silicon dioxide, respectively.
20. A method of forming vertically-stacked memory cells, comprising:
forming an opening to extend partially through a stack of alternating silicon dioxide levels and conductively-doped silicon levels;
forming a liner along sidewalls of the opening;
etching into the stack to extend the opening; the liner being at least partially consumed during the etch and forming passivation material; three zones occurring during the etch, with one of the zones being an upper zone of the opening protected by the liner, another of the zones being an intermediate zone of the opening protected by passivation material but not the liner, and another of the zones being a lower zone of the opening which is not protected by either passivation material or the liner;
forming cavities extending into the conductively-doped silicon levels along sidewalls of the opening; and
forming charge blocking dielectric and charge-storage structures within the cavities.
21. The method of claim 20 wherein the liner is entirely consumed during the etch.
22. The method of claim 20 wherein the liner is only partially consumed during the etch.
23. The method of claim 20 wherein the liner comprises electrically conductive material and is entirely consumed during the etch.
24. method of claim 20 wherein the liner comprises one or more of silicon nitride, carbon and polycrystalline silicon.
25. The method of claim 20 wherein the liner comprises silicon nitride over polycrystalline silicon; wherein the silicon nitride is entirely consumed during the etch but at least some of the polycrystalline of the liner remains after the etch; and wherein the remaining polycrystalline silicon of the liner is removed during the formation of the cavities.
26. The method of claim 20 wherein a ridge forms at a base of the liner and remains after the etch.