Scan test circuit, test pattern generation control circuit, and scan test control method
To improve a delay fault coverage without increasing an area overhead, provided is a scan test circuit including: scan flip-flops forming a clock domain that operates according to the same clock within a semiconductor integrated circuit including a target of a delay fault test; a test pattern generation mode control unit (scan flip-flop) that is supplied with the same clock as that supplied to the scan flip-flops, and selects one of a skewed-load mode and a broadside mode as a test pattern generation mode of the delay fault test; and a scan enable signal output unit (OR gate) that outputs a first scan enable signal, which is determined based on the test pattern generation mode, to the scan flip-flops.
1. A scan test circuit comprising:
a plurality of flip-flop circuits forming a clock domain that operates according to a same clock within a semiconductor integrated circuit including a target of a delay fault test;
a test pattern generation mode control unit that is supplied with the same clock as the clock supplied to the plurality of flip-flop circuits, and selects one of a skewed-load mode and a broadside mode as a test pattern generation mode of the delay fault test; and
a scan enable signal output unit that outputs a first scan enable signal to the plurality of flip-flop circuits, the first scan enable signal being determined based on the test pattern generation mode.
2. The scan test circuit according to claim 1 , wherein the scan enable signal output unit performs an OR operation using, as input values, the first scan enable signal and a second scan enable signal output from an external circuit, and outputs a result of the OR operation to the plurality of flip-flop circuits as a third scan enable signal.
3. The scan test circuit according to claim 1 , further comprising a toggle value control unit that performs a scan-shift operation on a toggle value set to cause a value held in a first flip-flop circuit to transit and outputs the toggle value to the first flip-flop circuit,
wherein when the test pattern generation mode is the skewed-load mode, the first flip-flop circuit holds the value to be output to a path serving as the target of the delay fault among the plurality of flip-flop circuits.
4. The scan test circuit according to claim 3 , wherein when the test pattern generation mode is the broadside mode, the first flip-flop circuit operates to enable use of a value output from a combinational circuit as the toggle value, the combinational circuit being configured to perform an operation with a combination of values output from the plurality of flip-flop circuits.
5. The scan test circuit according to claim 1 , wherein the test pattern generation mode control unit comprises a reset-function-equipped multiplexer-type scan flip-flop circuit.
6. The scan test circuit according to claim 3 , wherein the toggle value control unit comprises one of a multiplexer-type scan flip-flop circuit and a D-flip-flop circuit.
7. The scan test circuit according to claim 1 , further comprising a capture-clock-time scan enable control unit provided to an input unit of the test pattern generation mode control unit,
wherein during the skewed-load mode:
the test pattern generation mode control unit causes the first scan enable signal to transit according to a launch clock, and
the capture-clock-time scan enable control unit operates to cause the first scan enable signal to transit according to a capture clock.
8. The scan test circuit according to claim 7 , wherein:
the test pattern generation mode control unit comprises a D-flip-flop circuit, and
the capture-clock-time scan enable control unit comprises a multiplexer-type scan flip-flop circuit.
9. A test pattern generation control circuit comprising:
a test pattern generation mode control unit that is supplied with a clock identical to a clock supplied to a plurality of flip-flop circuits forming a clock domain operating according to a same clock within a semiconductor integrated circuit including a path serving as a target of a delay fault test, and selects one of a skewed-load mode and a broadside mode as a test pattern generation mode of the delay fault test; and
a scan enable signal output unit that outputs a first scan enable signal to the plurality of flip-flop circuits, the first scan enable signal being determined based on the test pattern generation mode.
10. The test pattern generation control circuit according to claim 9 , wherein the scan enable signal output unit performs an OR operation using, as input values, the first scan enable signal and a second scan enable signal output from an external circuit, and outputs a result of the OR operation to the plurality of flip-flop circuits as a third scan enable signal.
11. The test pattern generation control circuit according to claim 9 , further comprising a toggle value control unit that performs a scan-shift operation on a toggle value set to cause a value held in a first flip-flop circuit to transit and outputs the toggle value to the first flip-flop circuit,
wherein when the test pattern generation mode is the skewed-load mode, the first flip-flop circuit holds the value to be output to the path serving as the target of the delay fault among the plurality of flip-flop circuits.
12. The test pattern generation control circuit according to claim 11 , wherein when the test pattern generation mode is the broadside mode, the first flip-flop circuit operates to enable use of a value output from a combinational circuit as the toggle value, the combinational circuit being configured to perform an operation with a combination of values output from the plurality of flip-flop circuits.
13. The test pattern generation control circuit according to claim 9 , wherein the test pattern generation mode control unit comprises a reset-function-equipped multiplexer-type scan flip-flop circuit.
14. The test pattern generation control circuit according to claim 11 , wherein the toggle value control unit comprises one of a multiplexer-type scan flip-flop circuit and a D-flip-flop circuit.
15. The test pattern generation control circuit according to claim 9 , further comprising a capture-clock-time scan enable control unit provided to an input unit of the test pattern generation mode control unit,
wherein during the skewed-load mode:
the test pattern generation mode control unit causes the first scan enable signal to transit according to a launch clock, and
the capture-clock-time scan enable control unit operates to cause the first scan enable signal to transit according to a capture clock.
16. The test pattern generation control circuit according to claim 15 , wherein:
the test pattern generation mode control unit comprises a D-flip-flop circuit, and
the capture-clock-time scan enable control unit comprises a multiplexer-type scan flip-flop circuit.
17. A scan test control method comprising:
supplying a clock identical to a clock supplied to a plurality of flip-flop circuits that form a clock domain operating according to a same clock within a semiconductor integrated circuit including a path serving as a target of a delay fault test, and selecting one of a skewed-load mode and a broadside mode as a test pattern generation mode of the delay fault test; and
outputting a scan enable signal to the plurality of flip-flop circuits, the scan enable signal being determined based on the test pattern generation mode.
18. The scan test circuit according to claim 7 , further comprising a capture-clock-time gated clock control unit that controls the clock supplied to the plurality of flip-flop circuits,
wherein during the skewed-load mode, the capture-clock-time gated clock control unit operates to prevent the capture clock from being supplied to the plurality of flip-flop circuits when the flip-flop circuits are controlled to capture data through a scan-in terminal based on the first scan enable signal.
19. The scan test circuit according to claim 18 , wherein:
the test pattern generation mode control unit comprises a D-flip-flop circuit,
the capture-clock-time scan enable control unit comprises a multiplexer-type scan flip-flop circuit, and
the capture-clock-time gated clock control unit comprises a multiplexer-type scan flip-flop circuit, a combinational circuit, and a clock gating cell.
20. The test pattern generation control circuit according to claim 15 , further comprising a capture-clock-time gated clock control unit that controls the clock supplied to the plurality of flip-flop circuits,
wherein during the skewed-load mode, the capture-clock-time gated clock control unit operates to prevent the capture clock from being supplied to the plurality of flip-flop circuits when the flip-flop circuits are controlled to capture data through a scan-in terminal based on the first scan enable signal.
21. The test pattern generation control circuit according to claim 20 , wherein:
the test pattern generation mode control unit comprises a D-flip-flop circuit,
the capture-clock-time scan enable control unit comprises a multiplexer-type scan flip-flop circuit, and
the capture-clock-time gated clock control unit comprises a multiplexer-type scan flip-flop circuit, a combinational circuit, and a clock gating cell.
22. The scan test circuit according to claim 18 , wherein:
a clock gating cell of the capture-clock-time gated clock control unit is provided in a logic circuit unit controlled using the test pattern generation mode control unit, and
during the skewed-load mode, when the plurality of flip-flop circuits is controlled to capture data through the scan-in terminal based on the first scan enable signal, the clock gating cell operates to prevent the capture clock from being supplied to the plurality of flip-flop circuits.
23. The scan test circuit according to claim 22 , wherein:
the test pattern generation mode control unit comprises a D-flip-flop circuit,
the capture-clock-time scan enable control unit comprises a multiplexer-type scan flip-flop circuit, and
the capture-clock-time gated clock control unit comprises a multiplexer-type scan flip-flop circuit and a combinational circuit.
24. The scan test circuit according to claim 22 , wherein:
the capture-clock-time gated clock control unit acquires a delay fault test mode signal for switching between a delay fault test mode and a stuck-at fault test mode, and
during the skewed-load mode, when the delay fault test mode is activated, the capture-clock-time gated clock control unit operates to prevent the capture clock from being supplied to the plurality of flip-flop circuits when the flip-flop circuits are controlled to capture data through the scan-in terminal based on the first scan enable signal.
25. The scan test circuit according to claim 24 , wherein:
the test pattern generation mode control unit comprises a -flip-flop circuit,
the capture-clock-time scan enable control unit comprises a multiplexer-type scan flip-flop circuit, and
the capture-clock-time gated clock control unit comprises a D-flip-flop circuit and a combinational circuit.
26. The scan test circuit according to claim 24 , wherein:
a clock gating cell is provided in the capture-clock-time gated clock control unit, and
during the skewed-load mode, when the plurality of flip-flop circuits is controlled to capture data through the scan-in terminal based on the first scan enable signal, the clock gating cell operates to prevent the capture clock from being supplied to the plurality of flip-flop circuits.
27. The scan test circuit according to claim 26 , wherein:
the test pattern generation mode control unit comprises a D-flip-flop circuit,
the capture-clock-time scan enable control unit comprises a multiplexer-type scan flip-flop circuit, and
the capture-clock-time gated clock control unit comprises a D-flip-flop circuit, a combinational circuit, and a clock gating cell.
28. The scan test circuit according to claim 18 , further comprising:
a first delay fault test pattern generation control circuit including the test pattern generation mode control unit and the capture-clock-time scan enable control unit; and
a second delay fault test pattern generation control circuit including the capture-clock-time gated clock control unit.
29. The scan test circuit according to claim 28 , wherein:
the test pattern generation mode control unit comprises a D-flip-flop circuit,
the capture-clock-time scan enable control unit comprises a multiplexer-type scan flip-flop circuit, and
the capture-clock-time gated clock control unit comprises a multiplexer-type scan flip-flop circuit, a D-flip-flop circuit, a combinational circuit, and a clock gating cell.
30. The test pattern generation control circuit according to claim 20 , further comprising:
a first delay fault test pattern generation control circuit including the test pattern generation mode control unit and the capture-clock-time scan enable control unit; and
a second delay fault test pattern generation control circuit including the capture-clock-time gated clock control unit.
31. The test pattern generation control circuit according to claim 30 , wherein:
the test pattern generation mode control unit comprises a D-flip-flop circuit,
the capture-clock-time scan enable control unit comprises a multiplexer-type scan flip-flop circuit, and
the capture-clock-time gated clock control unit comprises a multiplexer-type scan flip-flop circuit, a D-flip-flop circuit, a combinational circuit, and a clock gating cell.
32. The scan test circuit according to claim 24 , wherein the clock gating cell of the capture-clock-time gated clock control unit is caused to operate based on an externally supplied clock enable signal.
33. The scan test circuit according to claim 32 , wherein:
the test pattern generation mode control unit comprises a D-flip-flop circuit,
the capture-clock-time scan enable control unit comprises a multiplexer-type scan flip-flop circuit, and
the capture-clock-time gated clock control unit comprises a multiplexer-type scan flip-flop circuit, a combinational circuit, and a clock gating cell.
34. A scan test control method comprising:
supplying a clock identical to a clock supplied to a plurality of flip-flop circuits that form a clock domain operating according to a same clock within a semiconductor integrated circuit including a path serving as a target of a delay fault test, and selecting one of a skewed-load mode and a broadside mode as a test pattern generation mode of the delay fault test; and
outputting a scan enable signal to the plurality of flip-flop circuits to stop a supply of an unwanted capture clock signal to the plurality of flip-flop circuits, the scan enable signal being determined based on the test pattern generation mode.