Serial-to parallel converter using serially-connected stages

1. A method for converting serial data having a certain word size to parallel data, comprising the steps of:

generating segments from the serial data using serially-connected stages, wherein the segments have a predetermined bit size;

storing each of the segments into a selectively turned-on flip-flop of a final stage, wherein the final stage is serially connected to the stages, wherein the final stage has a plurality of flip-flops, wherein each of the flip-flops has a bit size equaling to the predetermined bit size, wherein the segments are latched to the flip-flops of the final stage according to generated clock signals, wherein selected ones of the flips-flops are activated by the generated clock signals to store up to the certain word size, and wherein non-selected ones of the flip-flops are deactivated by the generated clock signals; and

outputting the stored segments in parallel.

2. The method of claim 1 wherein the predetermined bit size is smaller than the certain word size.

3. The method of claim 1 wherein the serial data is received according to an external clock signal and wherein the generated clock signals are generated as a function of the external clock signal and the certain word size.

4. The method of claim 3 wherein the generated clock signals have a predefined frequency and wherein the predefined frequency is equal to the frequency of the external clock signal divided by the certain word size.

5. The method of claim 1 wherein if remaining bits of the serial data to be processed by the stages is less than the predetermined bit size of the segments, then a selected one of the stages outputs directly to the final stage, and wherein one or more intermediary stages bypass processing the remaining bits.

6. A serial-to-parallel converter for converting serial data having a certain word size to parallel data, comprising:

serially-connected stages, wherein the stages generate segments from the serial data and wherein the segments have a predetermined bit size; and

a final stage, wherein the final stage comprises flip-flops, wherein the final stage is serially connected to the stages, wherein each of the segments is stored into a selected one of the flip-flops, wherein each of the flip-flops has a bit size equaling to the predetermined bit size, and wherein the stored segments are outputted in parallel, wherein the segments are latched to the flip-flops of the final stage according to generated clock signals, wherein selected ones of the flips-flops are activated by the generated clock signals to store up to the certain word size, and wherein non-selected ones of the flip-flops are deactivated by the generated clock signals.

7. The serial-to-parallel converter of claim 6 wherein the predetermined bit size is smaller than the certain word size.

8. The serial-to-parallel converter of claim 6 wherein the serial data is received according to an external clock signal and wherein the generated clock signals are generated as a function of the external clock signal and the certain word size.

9. The serial-to-parallel converter of claim 8 wherein the generated clock signals have a predefined frequency and wherein the predefined frequency is equal to the frequency of the external clock signal divided by the certain word size.

10. The serial-to-parallel converter of claim 6 wherein if remaining bits of the serial data to be processed by the stages is less than the predetermined bit size of the segments, then a selected one of the stages outputs directly to the final stage, and wherein one or more intermediary stages bypass processing the remaining bits.

11. A method for converting serial data having a certain word size to parallel data, comprising the steps of:

generating segments from the serial data using serially-connected stages, wherein the segments have a predetermined bit size;

storing each of the segments into a selectively turned-on flip-flop of a final stage, wherein the final stage is serially connected to the stages, wherein the final stage has a plurality of flip-flops, and wherein each of the flip-flops has a bit size equaling to the predetermined bit size, wherein selected ones of the flips-flops are activated by the generated clock signals to store up to the certain word size and wherein non-selected ones of the flip-flops are deactivated by the generated clock signals; and

outputting the stored segments in parallel,

wherein the predetermined bit size is smaller than the certain word size,

wherein the segments are latched to the flip-flops of the final stage according to generated clock signals, and

wherein the serial data is received according to an external clock signal and wherein the generated clock signals are generated as a function of the external clock signal and the certain word size.

12. The method of claim 11 wherein the generated clock signals have a predefined frequency and wherein the predefined frequency is equal to the frequency of the external clock signal divided by the certain word size.

13. The method of claim 11 wherein if remaining bits of the serial data to be processed by the stages is less than the predetermined bit size of the segments, then a selected one of the stages outputs directly to the final stage, and wherein one or more intermediary stages bypass processing the remaining bits.