Current source circuits and methods for mass write and testing of programmable impedance elements

1. An integrated circuit (IC) device, comprising:

a plurality of memory cells, each including at least one element programmable between different impedance states by application of a voltage or current;

a plurality of bit line groups, each bit line group including multiple bit lines, each bit line being coupled to multiple memory cells;

a plurality of current source circuits coupled to the bit line groups, each current source circuit configured to couple the bit lines of its respective group to at least a first bias node or a second bias node;

a controller circuit configured to generate current source control signals in response to input mode data; and

the two current source circuits are configured to couple corresponding bit line groups to at least the first or second bias nodes in response to the current control signals.

2. The IC device of claim 1 , wherein:

the bit line groups include a first group that includes even bit lines and a second group that includes odd bit lines, the even bit lines alternating with the odd bit lines, and the even and odd bit lines being substantially parallel to one another; wherein

the even and odd bit lines include at least sixteen bit lines.

3. The IC device of claim 1 , wherein:

the memory cells are arranged into an array of rows and columns, the memory cells of a same column being coupled to the same bit line, the memory cells of the same row being coupled to a same word line.

4. The IC device of claim 3 , wherein:

each memory cell includes at least one access device configured to couple the element of the memory cell to the corresponding bit line in response to a signal on its corresponding word line.

5. The IC device of claim 1 , wherein:

the elements comprise conductive bridging random access memory (CBRAM) elements.

6. The IC device of claim 1 , wherein:

each current source circuit is further configured to couple its respective bit line group to a high impedance node.

7. The IC device of claim 1 , wherein:

the first bias node is configured to receive a high power supply voltage; and

the second bias node is configured to receive a low power supply voltage.

8. The IC device of claim 1 , further including:

the memory cells are arranged into an array of rows and columns, the memory cells of a same column being coupled to the same bit line, the memory cells of the same row being coupled to a same word line;

a row control circuit configured to access rows of memory cells in response to row control signals; and

the controller circuit further includes a row counter configured to generate a sequence of row control signals based on a row value generated in response to the row counter.

9. The IC device of claim 1 , further including:

the memory cells are arranged into an array of rows and columns, the memory cells of a same column being coupled to the same bit line, the memory cells of the same row being coupled to a same word line, each word line being activated in response to a row control signal; and

the controller circuit is configured to automatically write data into a sequence of rows and further includes a row counter that generates a sequence of row control signals in response to the row counter.

10. A method, comprising

coupling a first bit line group to one of a plurality of different bias nodes in response to a first control signal;

coupling a second bit line group to one of the different bias nodes in response to a second control signal; and

the first and second bit lines groups each include a plurality of bit lines, each bit line is coupled to a column of memory cells, and each memory cell includes at least one element programmable between at least two different impedance states; wherein,

the bias nodes include a first bias node configured to receive a first potential; and

coupling the first bit line group to the first bias node writes a first data value into memory cells coupled to the first bit line group.

11. The method of claim 10 , wherein:

the bias nodes include a second bias node configured to receive a second potential; and

coupling the second bit line group to the second bias node writes a second data value into memory cells coupled to the second bit line group.

12. The method of claim 10 , further including:

the memory cells are further arranged into rows;

for a first group of rows, coupling the first bit line group to a first of the bias nodes, and coupling the second bit line group to a second of the bias nodes; and

for a second group of rows, coupling the first bit line group to the second of the bias nodes, and coupling the second bit line group to the first of the bias nodes; wherein

the first bias node is biased to a first potential that writes a first data value into the memory cells, and the second bias node is biased to a second potential that writes a second data value into the memory cells.

13. The method of claim 12 , wherein:

the bit lines of the first bit line group alternate with the bit lines of the second bit line group in a row direction of a memory array;

the rows of the first group of rows alternate with the rows of the second group of rows in a column direction of the memory array; and

the method writes a checkerboard pattern into the array.

14. The method of claim 10 , wherein:

the bias nodes include a first bias node configured to receive a first potential;

coupling the first bit line group to the first bias node;

coupling the second bit line group to the first bias node; and

determining if a current through the bit lines is below a predetermined threshold to detect bit line related defects.

15. The method of claim 10 , wherein:

the bias nodes include a first bias node configured to receive a first potential and a high impedance bias node;

coupling the first bit line group to the first bias node;

coupling the second bit line group to the high impedance node; and

determining if a current through a bit line of the second bit line group is above a predetermined threshold to detect bit line related defects.

16. An integrated circuit (IC) device, comprising:

at least one memory cell array including memory cells arranged into rows and columns, memory cells of the same column being coupled to a same bit line, and each memory cell including at least one element programmable between different impedance states;

current source circuits disposed on one side of the memory cell array, each current source circuit configured to independently connect a different group of bit lines to one of a plurality of different bias nodes; and

column sensing circuits disposed on a side of the memory cell array opposite to the current source circuits, the column sensing circuits configured to sense currents flowing through the bit lines.

17. The IC device of claim 16 , wherein:

the bias nodes include

a first bias node configured to receive a first potential, and

a second bias node configured to receive a second potential that is lower than the first potential.

18. The IC device of claim 16 , further including:

the column sensing circuits to generate data values in response to the sense currents; and

a memory controller configured to control which bias voltages are applied to the bias node and including a test latch configured to store the data values from the columns sense circuit.

19. The IC device of claim 16 , further including:

a memory controller that includes

a row counter configured to generate row access values to access rows of memory cells according to a predetermined sequence; and

a column counter configured to generate column access values to access columns of memory cells according to a predetermined sequence.