Extended drain lateral DMOS transistor with reduced gate charge and self-aligned extended drain
View Patent ↗A method to form a LDMOS transistor includes forming a gate/source/body opening and a drain opening in a field oxide on a substrate structure, forming a gate oxide in the gate/source/body opening, and forming a polysilicon layer over the substrate structure. The polysilicon layer is anisotropically etched to form polysilicon spacer gates separated by a space in the gate/source/body opening and a polysilicon drain contact in the drain opening. A body region is formed self-aligned about outer edges of the polysilicon spacer gates, a source region is formed self-aligned about inner edges of the polysilicon spacer gates, and a drain region is formed under the polysilicon drain contact and self-aligned with respect to the polysilicon spacer gates. A drift region forms in the substrate structure between the body region and the drain region, and a channel region forms in the body region between the source region and the drift region.
1. A method to form a lateral double-diffused metal-oxide-semiconductor transistor, comprising:
forming a field oxide on a substrate structure;
using a single mask, concurrently forming a gate/source/body opening and a drain opening in the field oxide down to the substrate structure;
forming a gate oxide on exposed substrate structure surface in the gate/source/body opening;
forming a polysilicon layer over the substrate structure, the polysilicon layer covering the field oxide, the gate/source/body opening, and the drain opening, the polysilicon layer having a minimum thickness in the gate/source/body opening less than a width of the gate/source/body opening;
anisotropic ally etching the polysilicon layer down to the field oxide and a portion of the gate oxide, thereby forming polysilicon spacer gates in the gate/source/body opening and a polysilicon extended drain contact in the drain opening, the polysilicon spacer gates being separated by a space over a portion of the gate oxide, the polysilicon spacer gates having base widths that are determined by the minimum thickness of the polysilicon layer in the gate/source/body opening and a duration of the anisotropic etching;
forming a body region of a first conductivity in the substrate structure, the body region being self-aligned about outer edges of the polysilicon spacer gates;
forming a source region of a second conductivity in the body region, the source region being self-aligned about inner edges of the polysilicon spacer gates;
forming an extended drain region of the second conductivity in the substrate structure, the extended drain region being located under the polysilicon extended drain contact and self-aligned with respect to the polysilicon spacer gates, a drift region being formed in the substrate structure between the extended drain region and the body region, and a channel region being formed in the body region between the source region and the drift region.
2. The method of claim 1 , wherein the polysilicon layer having a minimum thickness in the drain opening greater than a width of the drain opening.
3. The method of claim 1 , wherein the extended drain region is formed through auto-doping from the polysilicon extended drain contact.
4. The method of claim 1 , further comprising forming a body contact to the body-region and a source contact to the source region.
5. The method of claim 1 , further comprising:
forming an other drain opening in the field oxide concurrently with forming the gate/source/body opening and the drain opening, wherein:
forming the polysilicon layer over the substrate structure includes covering the other drain opening; and
anisotropically etching the polysilicon layer includes forming an other polysilicon extended drain contact in the other drain opening; and
forming an other extended drain region of the second conductivity in the substrate structure, the other extended drain region being located under the other polysilicon extended drain contact, another drift region being formed in the substrate structure between the other extended drain region and the body region, and an other channel region being formed in the body region between the source region and the other drift region.
6. The method of claim 1 , wherein the gate/source/body opening and the drain opening comprise rectangular openings, and the polysilicon spacer gates are arranged against opposing sidewalls of the gate/source/body opening.
7. The method of claim 6 , wherein the polysilicon spacer gates each comprises a rounded profile.
8. The method of claim 7 , wherein the polysilicon spacer gates comprise base widths of about 0.2 to 0.25 microns.
9. The method of claim 1 , prior to forming the field oxide, further comprising:
forming the substrate structure, comprising:
growing an epitaxial layer of the second conductivity on a substrate of a first conductivity; and
forming a well of the second conductivity in the epitaxial layer, wherein the source region, the body region, and the extended drain region are located in the well.
10. The method of claim 1 , wherein forming the drain opening and the gate/source/body opening comprises:
masking the field oxide and removing portions of the field oxide over a gate/source/body area and an extended drain area on the substrate structure.
11. The method of claim 1 , further comprising, after forming the drain opening and the gate/source/body opening:
growing and removing a sacrificial oxide on exposed substrate structure surfaces in the gate/source/body opening and the drain opening.
12. The method of claim 1 , wherein forming the gate oxide comprises:
forming a gate oxide layer on exposed substrate structure surfaces in the gate/source/body opening and the drain opening; and
removing a portion of the gate oxide layer in the drain opening.
13. The method of claim 1 , further comprising, after forming the polysilicon layer and before anisotropically etching the polysilicon layer:
annealing and oxidizing the polysilicon layer.