Three dimensional non-volatile storage with interleaved vertical select devices above and below vertical bit lines

1. A non-volatile storage system, comprising:

a substrate;

a monolithic three dimensional array of memory cells positioned above and not in the substrate;

a plurality of signal lines;

a plurality of vertically oriented bit lines that are above and not in the substrate, the vertically oriented bit lines are connected to the array of memory cells;

a plurality of vertically oriented select devices that are above the substrate but not in the substrate, the vertically oriented select devices are connected to the vertically oriented bit lines and the signal lines, a first subset of the vertically oriented select devices are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices are positioned below the vertically oriented bit lines in an interleaved manner such that every other vertically oriented select device along a first direction are positioned above the vertically oriented bit lines with intervening vertically oriented select devices positioned below the vertically oriented bit lines, when the vertically oriented select devices are actuated the vertically oriented bit lines are in communication with the signal lines;

a plurality of word lines connected together and connected to a set of the memory cells, the word lines connected together form a first word line comb having multiple word line fingers, and

a controller for choosing slices of memory cells for a concurrent memory operation based on the slices being connected to the first word line comb but on different fingers of the first word line comb, at least one of the slices interacts with the vertically oriented bit lines that connect to a first subset of the signal lines including global bit lines positioned above the vertically oriented bit lines and the other at least one slice interacts with vertically oriented bit lines connecting to a second subset of the signal lines including global bit lines positioned below the vertically oriented bit lines.

2. The non-volatile storage system of claim 1 , further comprising:

the plurality of word lines connected together and connected to the set of the memory cells, the memory cells in combination with the vertically oriented bit lines and the word lines form a continuous mesh.

3. The non-volatile storage system of claim 2 , further comprising:

a word line driver in the substrate, below the set of the memory cells and in communication with the word lines connected together.

4. The non-volatile storage system of claim 2 , wherein:

the first word line comb is interleaved with two other word line combs.

5. The non-volatile storage system of claim 2 , wherein:

the monolithic three dimensional memory array of memory cells includes memory cells on multiple levels; and

the word lines connected together are on a common plane and the set of memory cells are on a common level.

6. The non-volatile storage system of claim 1 , further comprising:

a plurality of select lines arranged as sidewalls to the vertically oriented select devices and used to actuate the vertically oriented select devices.

7. The non-volatile storage system of claim 1 , wherein:

the vertically oriented select devices are wider than the vertically oriented bit lines.

8. The non-volatile storage system of claim 1 , wherein:

the vertically oriented select devices are twice as wide as the vertically oriented bit lines.

9. A method for operating a non-volatile storage system, comprising:

applying an unselected word line voltage to a plurality of word lines connected to a monolithic three dimensional array of memory cells positioned above and not in a substrate;

applying an unselected bit line voltage to a plurality of global bit lines, the global bit lines are connected to a plurality of vertically oriented select devices that are above the substrate but not in the substrate, the vertically oriented select devices are also connected to vertically oriented bit lines which are connected to the array of memory cells, a first subset of the vertically oriented select devices are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices are positioned below the vertically oriented bit lines in an interleaved manner such that every other vertically oriented select device along a first direction are positioned above the vertically oriented bit lines with intervening vertically oriented select devices positioned below the vertically oriented bit lines;

choosing slices of memory cells for a concurrent memory operation based on the slices being connected to a first word line comb but on different fingers of the first word line comb, at least one of the slices interacts with the vertically oriented bit lines that connect to a first subset of the global bit lines positioned above the vertically oriented bit lines and the other at least one slice interacts with vertically oriented bit lines connecting to a second subset of the global bit lines positioned below the vertically oriented bit lines;

applying a selected bit line voltage to one or more selected global bit lines;

applying an actuating signal to a first selection line connected to the first subset of the vertically oriented select devices that are positioned above the vertically oriented bit lines;

applying an actuating signal to a second selection line connected to the second subset of the vertically oriented select devices that are positioned below the vertically oriented bit lines; and

applying a selected word line voltage to the first word line comb so that the concurrent memory operation is performed for the chosen slices of memory cells.

10. The method of claim 9 , wherein:

the vertically oriented select devices are on top of and are wider than the vertically oriented bit lines.

11. The method of claim 9 , wherein:

the applying an actuating signal to a first selection line comprises applying the actuating signal to a side wall of the first subset of the vertically oriented select devices to actuate the first subset of the vertically oriented select devices; and

the applying an actuating signal to a second selection line comprises applying the actuating signal to a side wall of the second subset of the vertically oriented select devices to actuate the second subset of the vertically oriented select devices.

12. A non-volatile storage system, comprising:

a plurality of non-volatile storage elements;

a plurality of signal lines;

a plurality of vertically oriented bit lines that are connected to the non-volatile storage elements;

a plurality of vertically oriented select devices that are connected to the vertically oriented bit lines and the signal lines, a first subset of the vertically oriented select devices are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices are positioned below the vertically oriented bit lines in an interleaved manner such that every other vertically oriented select device along a first direction are positioned above the vertically oriented bit lines with intervening vertically oriented select devices positioned below the vertically oriented bit lines, when the vertically oriented select devices are actuated the vertically oriented bit lines are in communication with the signal lines;

a plurality of word lines connected together and connected to a set of the memory cells, the word lines connected together form a first word line comb having multiple word line fingers, and

a controller for choosing slices of memory cells for a concurrent memory operation based on the slices being connected to the first word line comb but on different fingers of the first word line comb, at least one of the slices interacts with the vertically oriented bit lines that connect to a first subset of the signal lines including global bit lines positioned above the vertically oriented bit lines and the other at least one slice interacts with vertically oriented bit lines connecting to a second subset of the signal lines including global bit lines positioned below the vertically oriented bit lines.

13. The non-volatile storage system of claim 12 , wherein:

the first word line comb is interleaved with two other word line combs.

14. The non-volatile storage system of claim 12 , further comprising:

a plurality of select lines arranged as sidewalls to the vertically oriented select devices and used to actuate the vertically oriented select devices.