Shared bit line SMT MRAM array with shunting transistors between bit lines
View Patent ↗An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.
1. An SMT MRAM device comprising:
SMT MRAM memory cells arranged in an array of rows and columns such that each of the columns of SMT MRAM cells is associated with one of its adjacent columns of SMT MRAM cells;
a plurality of true data bit lines where each of the true data bit lines is connected to one adjacent column;
a plurality of complement data bit lines, wherein each of the plurality of complement data bit lines are connected with each SMT MRAM cell of a pair of columns of the SMT MRAM cells such that each of the plurality of complement data bit lines is shared with the pair of columns of the SMT MRAM cells; and
a plurality of shunting switch devices, wherein each of the shunting switch devices is connected between one of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.
2. The SMT MRAM device of claim 1 further comprising a column address decoder in communication with an activation terminal of each of the shunting switch devices such that the shunting switch device is activated to connect the true data bit line associated with the non-selected column in parallel with the complement data bit line.
3. The SMT MRAM device of claim 1 wherein the shared complement data bit line is wider than the true data bit line to further lower the resistance of the shared complement data bit line.
4. The SMT MRAM device of claim 3 wherein the shared complement data bit line is twice the dimension of the true data bit line.
5. The array of SMT MRAM cells of claim 3 further comprising means for selectively connecting the two adjacent complement bit lines in parallel to merge the two adjacent complement bit lines to appear much wider and therefore less resistive to permit a larger and more area efficient array of SMT MRAM cells.