Shared bit line SMT MRAM array with shunting transistors between bit lines
View Patent ↗An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.
1. A bit line structure for connecting columns of SMT MRAM cells within an array of SMT MRAM cells arranged in rows and columns comprising
a true data bit line connected to an MTJ device of each SMT MRAM cell of a column of the SMT MRAM cells
a complement data bit line connected to a source of a gating transistor of each SMT MRAM cell of a pair of associated columns of the SMT MRAM cells
at least one shunting switch transistor connected between the true data bit line and the complement data bit line of the associated pair of columns of the SMT MRAM cells such that the at least one shunting switch transistor has an activation terminal that, when activated, connects the true data bit line of an unselected column of the SMT MRAM cells in parallel with the shared complement data bit line to effectively reduce program disturb effects in the unselected column of SMT MRAM cells.
2. The bit line structure of claim 1 wherein the shared complement data bit line is wider than the true data bit line to further lower the resistance of the shared complement data bit line.
3. The bit line structure of claim 1 wherein the shared complement data bit line may be twice the dimension of the true data bit line.