Test circuitry coupled to embedded circuit input/output unconnected to pads
Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.
1. A die of semiconductor material, comprising:
A. die pads arranged at the periphery of the die;
B. a first embedded circuit having functional inputs and outputs, at least one of the functional inputs and at least one of the functional outputs being unconnected to a die pad;
C. test circuitry coupled to the one of the functional inputs of the first embedded circuit that is unconnected to a die pad, the one of the functional outputs of the first embedded circuit that is unconnected to a die pad; and the test circuitry having an enable input; and
D. test enable circuitry having an input connected to an enable test pad, separate from the die pads, and an output coupled to the test circuitry enable input.
2. The die of claim 1 in which the test circuitry includes a first test isolation buffer coupled to the one of the functional inputs and a second test isolation buffer coupled to the one of the functional outputs, and the test enable circuitry includes a series connection of an input buffer having an input connected to the enable test pad, a first OR gate having an output connected to the first test isolation buffer, and a second OR gate having an output connected to the second test isolation buffer.
3. The die of claim 1 in which the embedded circuit is one of a digital signal processor core, a microprocessor core, mixed signal circuitry, peripheral circuitry, and memory circuitry.