FPGA RAM blocks optimized for use as register files
A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described.
1. A field programmable gate array integrated circuit device comprising:
a programmable array having logic modules and horizontal and vertical routing interconnects programmably coupleable to the logic modules;
a random access memory circuit having a number of external input terminals coupleable to the logic modules, the random access memory circuit including at least one port, the at least one port comprising a plurality of address inputs, and a plurality of data inputs, a total number of data inputs and address inputs exceeding the number of external input terminals;
at least one random access memory interface cluster disposed between the programmable array, the random access memory interface cluster connected on an array side to a first number of the horizontal and vertical routing interconnects and connected to a random access memory circuit side to the external input terminals of the random access memory circuit, the first number of the horizontal and vertical routing interconnects being less than the number of external input terminals;
wherein on the random access memory side of the random access memory interface cluster at least one external input terminal of the random access memory circuit is hardwired to one address input and one data input of the random access memory circuit.
2. The field programmable gate array integrated circuit device of claim 1 , wherein at least one address or data input is driven by either of two shared external input terminals through a multiplexer disposed on the random access memory side of the random access memory interface cluster.
3. The field programmable gate array integrated circuit device of claim 1 wherein the at least one port is readable and asynchronous.
4. The field programmable gate array integrated circuit device of claim 1 comprising two ports, each of the the two ports comprising a plurality of address inputs each programmably coupleable to the routing interconnects and a plurality of data outputs each programmably coupleable to the routing interconnects.
5. The field programmable gate array integrated circuit device of claim 4 wherein the two ports are readable and asynchronous.
6. The field programmable gate array integrated circuit device of claim 1 further comprising a writable port in the random access memory circuit, the writable port including a plurality of data inputs each programmably coupleable to the routing interconnects.
7. The field programmable gate array integrated circuit device of claim 6 , wherein the writable port of the random access memory circuit is synchronous.