IP Library Granted Patent US 9,130,003
Granted Patent B2
US 9,130,003 · App. 13/899,858 · Granted Sep 8, 2015

Structure for picking up a collector and method of manufacturing the same

Inventor: Wensheng Qian (Shanghai, CN)
Assignee: SHANGHAI HUA HONG NEC ELECTRONICS
H01L29/73H01L29/0821H01L29/66234H01L29/66242H01L29/7378H01L21/763H01L29/41708
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Quick Facts
Patent No.
US 9,130,003
App. No.
13/899,858
Granted
Sep 8, 2015
Kind
B2
Abstract

A structure for picking up a collector region including a pair of polysilicon stacks formed in the isolation regions and extending below the collector region; and a pair of collector electrodes contacting on the polysilicon stacks, wherein the pair of polysilicon stacks includes: an undoped polysilicon layer and a doped polysilicon layer located on the undoped polysilicon layer, wherein a depth of the doped polysilicon layer is greater than a depth of the collector region; the depth of the collector region is greater than a depth of the isolation regions.

Claims (29)

1. A structure for picking up a collector region, the collector region being formed in a substrate and having a core portion located between two isolation regions and a lateral portion adjacent to and underlying each of the two isolation regions, the structure comprising:

a pair of polysilicon stacks formed in the substrate and extending downward through the isolation regions into a depth greater than a depth of the collector region, the pair of polysilicon stacks comprising an undoped polysilicon layer and a doped polysilicon layer located on the undoped polysilicon layer, the doped polysilicon layer having an opposite conductivity type to a conductivity type of the substrate; and

a pair of collector electrodes contacting on the polysilicon stacks,

wherein the depth of the collector region is smaller than a depth of the doped polysilicon layer and greater than a depth of the isolation regions, the doped polysilicon layer having a side face contacting with the lateral portion of the collector region.

2. The structure according to claim 1 , further comprising an intermediate layer formed between the undoped polysilicon layer and the doped polysilicon layer.

3. The structure according to claim 1 , wherein the doped polysilicon layer has a depth great enough to ensure a low parasitic capacitance between the doped polysilicon layer and the substrate.

4. The structure according to claim 2 , wherein the doped polysilicon layer has a depth great enough to ensure a low parasitic capacitance between the doped polysilicon layer and the substrate.

5. A method of manufacturing the structure for picking up a collector region according to claim 1 , the method comprising:

forming two isolation regions in a substrate, the isolation regions isolating an active region therebetween;

forming a trench through each of the isolation regions, each trench extending below the isolation regions;

depositing an undoped first polysilicon to completely fill the trenches;

removing a portion of the first polysilicon in an upper portion of each trench so that the remaining first polysilicon serves as the undoped polysilicon layer;

depositing a second polysilicon to form the doped polysilicon layer in the upper portion of each trench;

forming a collector region between the two isolation regions, both sides of the collector region contacting a first side face of the doped polysilicon layer, a depth of the collector region being smaller than a depth of the doped polysilicon layer and greater than a depth of the isolation regions; and

forming collector electrodes contacting on the doped polysilicon layer.

6. The method according to claim 5 , wherein the second polysilicon is in-situ doped with a dopant that has an opposite conductivity type to the substrate during the process of depositing the second polysilicon.

7. The method according to claim 5 , wherein the second polysilicon is doped by ion implantation with a dopant that has an opposite conductivity type to the substrate after the second polysilicon is deposited.

8. A method of manufacturing the structure for picking up a collector region according to claim 2 , the method comprising:

forming two isolation regions in a substrate, the isolation regions isolating an active region therebetween;

forming a trench through each of the isolation regions, each trench extending below the isolation regions;

depositing an undoped first polysilicon to completely fill the trenches;

removing a portion of the first polysilicon in an upper portion of each trench so that the remaining first polysilicon serves as the undoped polysilicon layer;

depositing an intermediate dielectric layer in the trenches to form an intermediate layer;

depositing a second polysilicon to completely fill the trenches to form the doped polysilicon layer in the upper portion of each trench;

forming a collector region between the two isolation regions, both sides of the collector region contacting a first side face of the doped polysilicon layer, a depth of the collector region being smaller than a depth of the doped polysilicon layer and greater than a

depth of the isolation regions; and

forming collector electrodes contacting on the doped polysilicon layer.

9. The method according to claim 8 , wherein the second polysilicon is in-situ doped with a dopant that has an opposite conductivity type to the substrate during the process of depositing the second polysilicon.

10. The method according to claim 8 , wherein the second polysilicon is doped by ion implantation with a dopant that has an opposite conductivity type to the substrate after the second polysilicon is deposited.

Assignments (2)
MERGER Recorded May 13, 2014
From: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.
To: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 032885/0047 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 22, 2013
From: QIAN, WENSHENG
To: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD
Reel/Frame 030465/0873 →
Priority Claims (1)
CN 2012 1 0163783 · May 23, 2012 · national
Continuity (1)
Related Publication 20130328047A1 · Dec 12, 2013