IP Library Granted Patent US 8,723,221
Granted Patent B2
US 8,723,221 · App. 13/899,896 · Granted May 13, 2014

Monolithic three terminal photodetector

Inventors: Yun-chung N. Na (Hsinchu, TW); Yimin Kang (San Jose, CA)
Assignee: Intel Corporation
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Quick Facts
Patent No.
US 8,723,221
App. No.
13/899,896
Granted
May 13, 2014
Kind
B2
Abstract

Photodetectors operable to achieve multiplication of photogenerated carriers at ultralow voltages. Embodiments include a first p-i-n semiconductor junction combined with a second p-i-n semiconductor junction to form a monolithic photodetector having at least three terminals. The two p-i-n structures may share either the p-type region or the n-type region as a first terminal. Regions of the two p-i-n structures doped complementary to that of the shared terminal form second and third terminals so that the first and second p-i-n structures are operable in parallel. A multiplication region of the first p-i-n structure is to multiply charge carriers photogenerated within an absorption region of the second p-i-n structure with voltage drops between the shared first terminal and each of the second and third terminals being noncumulative.

Claims (17)

1. A photodetector circuit, comprising:

a first p-i-n structure coupled to a first terminal and to a second terminal;

a second p-i-n structure coupled to the first terminal and to a third terminal; and

one or more voltage supplies coupled across the first, second and third terminals to reverse bias the first and the second p-i-n structures in parallel, wherein the one or more voltage supplies are to provide a reverse bias across the first p-i-n structure sufficient to induce carrier multiplication within the first p-i-n structure, and wherein the one or more voltage supply are to provide a reverse bias across the second p-i-n structure sufficient to induce carrier drift within the second p-i-n structure.

2. The photodetector circuit of claim 1 , wherein the one or more voltage supplies are a single voltage supply, wherein the second and third terminals are both coupled to a common node at a reference voltage, and wherein a first i-layer is dimensioned to induce the carrier multiplication at the reverse bias provided across the first and second terminals by the single voltage supply.

3. The photodetector circuit of claim 2 , and wherein the one or more voltage supply provides less than 6V across the first and second terminals.

4. The photodetector circuit of claim 2 , wherein the first terminal is coupled through a first of n-type and p-type regions of the first and second p-i-n structures, the second and third terminals are coupled through the other of the n-type and p-type regions of the first and second p-i-n structures.

5. The photodetector circuit of claim 2 , wherein the first terminal is coupled through the n-type regions of the p-i-n structures, the second and third terminals are coupled through the p-type regions of the p-i-n structures.

6. The photodetector circuit of claim 1 , wherein the first p-i-n structure comprises an arrayed plurality of n-type regions interdigitated with a plurality of the p-type regions with lighter doped i-layers disposed there between, each of the n-type regions coupled to the first terminal and each of the p-type regions coupled to the second terminal.

7. The photodetector circuit of claim 6 , wherein the second p-i-n structure comprises a semiconductor material stack oriented orthogonally to the first p-i-n structure.

8. The photodetector circuit of claim 7 , wherein the second p-i-n structure is optically coupled a waveguide.

9. The photodetector circuit of claim 7 , wherein the first p-i-n structure extends laterally over an area of a substrate and wherein the second p-i-n structure extends vertically over or under the first p-i-n structure and monolithically integrated onto the substrate.

10. The photodetector circuit of claim 7 , wherein the first group IV semiconductor is one of Si, Ge, or a Si x Ge y alloy and wherein the second group IV semiconductor is another of Si, Ge, or Si x Ge y alloy.

11. The photodetector circuit of claim 10 , wherein the first p-i-n structure is Si and wherein the second p-i-n structure is Ge.

12. The photodetector circuit of claim 1 , wherein the second p-i-n structure comprises:

an absorption i-layer disposed over the first p-i-n structure; and

a p-type layer coupled to the third terminal.

Assignments (1)
CONFIRMATORY LICENSE Recorded Feb 19, 2015
From: INTEL CORPORATION
To: DARPA
Reel/Frame 034988/0701 →
Continuity (2)
Division 12952023 · Nov 22, 2010
Related Publication 20140077327A1 · Mar 20, 2014