Granted Patent B2

US 8,975,943 · App. 13/904,941 · Granted Mar 10, 2015

Abstract

Claims (91)

1. A device for level shifting an input signal comprising:

an output buffer having an output node, a p-type field effect transistor coupled to a high reference voltage, and an n-type field effect transistor coupled to a low reference voltage;

a first latch having a first latch output, said first latch output driving a gate of said p-type field effect transistor via an inverting circuit element;

a second latch having a second latch output, said second latch output driving a gate of said n-type field effect transistor; and

a reset signal pulse generator receiving said input signal and generating a reset signal pulse in response to: (1) a transition in said input signal from a high input voltage to a low input voltage, and (2) a transition in said input signal from said low input voltage to said high input voltage;

wherein both said first and said second latches are placed in a reset state by said reset signal pulse.

2. The device of claim 1 , wherein:

said high reference voltage is higher than said high input voltage;

said low reference voltage is lower than said low input voltage;

said first latch output is set to a ground voltage when placed in said reset state; and

said second latch output is set to said low reference voltage when placed in said reset state.

3. The device of claim 1 , further comprising:

a second output buffer having an inverted output node, a second p-type field effect transistor coupled to said high reference voltage and an n-type field effect transistor coupled to said low reference voltage;

wherein:

a complementary first output of said first latch drives a gate of said second p-type field effect transistor via a second inverting circuit; and

a complementary second output of said second latch drives a gate of said second n-type field effect transistor.

4. The device of claim 3 , said first latch comprising:

a pair of p-type field effect transistors having: (1) a shared source connection and (2) cross-coupled gate and drain connections, said cross-coupled connections being separately connected to a positive first latch output and a negative first latch output; and

a pair of n-type field effect transistors having a shared source connection to said ground voltage;

wherein:

said positive first latch output is said first latch output; and

said negative first latch output is said complementary first output of said first latch.

5. The device of claim 4 , said first latch further comprising:

a depletion mode transistor having a drain connection to said high reference voltage, a gate connection to said shared source connection of said pair of p-type field effect transistors, and a drain connection to said shared source connection of said pair of p-type field effect transistors;

wherein said reset signal pulse drives a gate of both n-type field effect transistors in said pair of n-type field effect transistors to said ground voltage.

6. The device of claim 3 , said second latch comprising:

a pair of inverters having a shared p-type source connection, a shared n-type source connection, and a pair of cross-coupled input and output nodes;

a pair of n-type field effect transistors having a shared source connection to said low reference voltage, each n-type field effect transistor in said pair of n-type field effect transistors being separately connected to one of said cross-coupled input and output nodes in said pair of cross-coupled input and output nodes;

wherein one of said cross-coupled input and output nodes in said pair of cross-coupled input and output nodes is said second latch output.

7. The device of claim 6 , said second latch further comprising:

a p-type field effect transistor having a source connection to said ground voltage, a gate node, and a drain connection to said shared p-type source connection of said pair of inverters;

wherein said reset signal pulse drives said gate node to said ground voltage and drives a gate of both n-type field effect transistors in said pair of n-type field effect transistors to said low reference voltage.

8. The device of claim 7 , wherein said gate node is driven to said low reference voltage in the absence of said reset signal pulse.

9. A process comprising:

driving an output node between a first voltage and a second voltage using a first buffer output device and a second buffer output device;

receiving a transition in an input signal, said transition being between an old state at a third voltage and a new state at a fourth voltage;

impeding said new state from being latched, temporarily, using a clear pulse that clears a state of a latch;

latching said input signal using said latch, said input signal setting an output state of said latch; and

driving a control node of said first buffer output device according to said output state of said latch;

wherein a magnitude of said first voltage is greater than a magnitude of said third voltage.

10. The process of claim 9 , further comprising:

latching said input signal using a second latch, said input signal setting an output state of said second latch; and

driving a control node of said second buffer output device according to an output state of said second latch;

wherein:

a magnitude of said second voltage is greater than a magnitude of said fourth voltage; and

said clear pulse clears a state of said second latch.

11. The process of claim 10 , wherein:

said first buffer output device is a p-type field effect transistor; and

said second buffer output device is an n-type field effect transistor.

12. The process of claim 9 , further comprising:

generating said clear pulse using a clock signal; and

delivering said clear pulse to said latch prior to receiving said transition in said input signal.

13. The process of claim 9 , further comprising generating said clear pulse from said transition in said input signal using a delay element.

14. An apparatus for increasing a magnitude of an input signal, comprising:

a first output buffer device connected to a high supply voltage and coupled to an output node;

a second output buffer device connected to a low supply voltage and coupled to said output node;

a core circuit having a reset state, a high state, and a low state; and

a reset pulse generator coupled to said core circuit;

wherein:

said core circuit places: (1) said first and second output buffer devices in nonconductive states when in said reset state; (2) said first output buffer device in a conductive state and said second output buffer device in a nonconductive state when in said high state; and (3) said first output buffer device in a nonconductive state and said second output buffer in a conductive state when in said low state;

said reset pulse generator places said core circuit in said reset state upon a transition in said input signal between a low input voltage and a high input voltage; and

a difference between said high input voltage and said low input voltage is smaller than a difference between said high supply voltage and said low supply voltage.

15. The apparatus of claim 14 , said reset pulse generator comprising:

a delay element connected to said input signal, said delay element producing a delayed input signal;

wherein:

said reset pulse generator generates a reset pulse from said delayed input signal; and

said reset pulse places said core circuit in said reset state faster than said core circuit can respond to a transition in said input signal.

16. The apparatus of claim 14 , wherein:

said first output buffer device is a p-type field effect transistor, said p-type field effect transistor being source connected to said high voltage supply and gate connected to said core circuit at a p-type gate node; and

said second output buffer device is an n-type field effect transistor; said n-type field effect transistor being source connected to said low voltage supply and gate connected to said core circuit at an n-type gate node.

17. The apparatus of claim 16 , wherein:

said low supply voltage is lower that said low input voltage; and

said high supply voltage is higher than said high input voltage.

18. The apparatus of claim 17 , said core circuit comprising:

a first latch having a first latch output and being coupled between said high supply voltage and a ground voltage; and

a second latch having a second latch output and being coupled between said ground voltage and said low supply voltage;

wherein:

said first latch output drives said p-type gate node towards said high supply voltage when said core circuit is in said reset state; and

said second latch output drives said n-type gate node towards said low supply voltage when said core circuit is in said reset state.

19. The apparatus of claim 18 , further comprising:

a third buffer output device connected to a high supply voltage node and coupled to an inverted output node;

a fourth buffer output device connected to a low supply voltage node and coupled to said inverted output node;

a third latch output for said first latch, said third latch output and said first latch output being differential outputs for said first latch; and

a fourth latch output for said second latch; said fourth latch output and said second latch output being differential outputs for said second latch;

wherein:

said third latch output places said third buffer output device in a nonconductive state when said core circuit is in said reset state; and

said fourth latch output places said fourth buffer output device in a nonconductive state when said core circuit is in said reset state.

20. The apparatus of claim 19 , wherein:

said p-type field effect transistor is drain connected to a first isolation transistor;

said n-type field effect transistor is drain connected to a second isolation transistor; and

said first and said second isolation transistors are connected to said output node.

Assignments (6)