Hybrid hard mask for damascene and dual damascene

1. A method, comprising:

forming a damascene conductor in a dielectric layer on a semiconductor substrate and a dielectric barrier layer on a top surface of said damascene conductor and a top surface of said dielectric layer;

forming a dielectric stack on a top surface of said dielectric barrier layer, said dielectric stack comprising an interlevel dielectric layer on a top surface of said dielectric barrier layer;

forming a lower hard mask layer on a top surface of said dielectric stack and an upper hard mask layer on a top surface of said lower hard mask layer;

using a first reactive ion etch selective to said upper and lower hard mask layers over said interlevel dielectric layer, forming a via opening through said upper hard mask layer and said lower hard mask layer to a top surface of said dielectric stack;

using a second reactive ion etch selective to said upper hard mask layer and said interlevel dielectric layer over said dielectric barrier layer, extending said via opening through said interlevel dielectric layer to said dielectric barrier layer;

removing said lower hard mask layer using a wet etch;

using a third reactive ion etch selective to said dielectric barrier layer over said damascene conductor and said interlevel dielectric layer to said damascene conductor, extending said via opening through said dielectric barrier layer to said damascene conductor; and

filling said via opening with an electrical conductor.

2. The method of claim 1 , wherein said upper hard mask layer comprise a metal nitride and said lower hard mask layer comprises a metal oxide or metal oxynitride.

3. The method of claim 1 , wherein said upper hard mask layer comprise titanium nitride and said lower hard mask layer comprises a titanium oxide or titanium oxynitride, said damascene conductor comprises tungsten or copper and said interlevel dielectric layer comprises an ultra low K material have a dielectric constant of 2.7 or less.

4. The method of claim 1 , wherein said wet etch comprises an aqueous solution of hydrogen fluoride and citric acid.

5. The method of claim 1 , further including:

between said forming said upper hard mask layer and performing said first reactive ion etch forming a patterned photoresist layer on a top surface of upper hard mask layer, an opening in said patterned hard mask layer defining a perimeter of said via opening and removing said patterned hard mask layer using said second reactive ion etch; or

between said forming said upper hard mask layer and performing said first reactive ion etch, forming an additional hardmask layer on a top surface of said upper hardmask layer, forming a patterned photoresist layer on a top surface of additional hard mask layer, using said patterned photoresist layer forming an opening in said additional hardmask layer using an additional reactive ion etch, removing said patterned photoresist layer, said opening in said additional hardmask layer defining a perimeter of said via opening, said first reactive ion etch selective to said upper and lower hardmask layers over said additional hardmask layer, said second reactive ion etch removing said additional hardmask layer.

6. The method of claim 1 , wherein:

said interlevel dielectric layer includes a dielectric capping layer on a top surface of said interlevel dielectric layer and said lower hard mask layer is formed on a top surface of said dielectric capping layer;

said first reactive ion etch is also selective to said upper and lower hard mask layers over said dielectric capping layer and extends said opening to said dielectric capping layer;

said second reactive ion etch is also selective to said dielectric capping layer over said dielectric barrier layer and extends said opening through said dielectric capping layer; and

said third reactive ion etch is also selective to said dielectric barrier layer over said dielectric capping layer.

7. The method of claim 6 , wherein said upper hard mask layer comprise a metal nitride and said lower hard mask layer comprises a metal oxide or metal oxynitride.

8. The method of claim 6 , wherein said upper hard mask layer comprise titanium nitride and said lower hard mask layer comprises a titanium oxide or titanium oxynitride, said damascene conductor comprises tungsten or copper and said interlevel dielectric layer comprises an ultra low K material have a dielectric constant of 2.7 or less.

9. The method of claim 6 , wherein said wet etch comprises an aqueous solution of hydrogen fluoride and citric acid between 22° C. and 70° C.

10. The method of claim 6 , further including:

between said forming said upper hard mask layer and performing said first reactive ion etch forming a patterned photoresist layer on a top surface of upper hard mask layer, an opening in said patterned hard mask layer defining a perimeter of said via opening and removing said patterned hard mask layer using said second reactive ion etch; or

between said forming said upper hard mask layer and performing said first reactive ion etch, forming an additional hardmask layer on a top surface of said upper hardmask layer, forming a patterned photoresist layer on a top surface of additional hard mask layer, using said patterned photoresist layer forming an opening in said additional hardmask layer using an additional reactive ion etch, removing said patterned photoresist layer, said opening in said additional hardmask layer defining a perimeter of said via opening, said first reactive ion etch selective to said upper and lower hardmask layers over said additional hardmask layer, said second reactive ion etch removing said additional hardmask layer.

11. A method, comprising:

forming a damascene conductor in a dielectric layer on a semiconductor substrate and a dielectric barrier layer on a top surface of said damascene conductor and a top surface of said dielectric layer;

forming a dielectric stack on a top surface of said dielectric barrier layer, said dielectric comprising an interlevel dielectric layer on a top surface of said dielectric barrier layer;

forming a lower hard mask layer on a top surface of said dielectric stack and an upper hard mask layer on a top surface of said lower hard mask layer;

using a first reactive ion etch selective to said upper and lower hard mask layers over said interlevel dielectric layer, forming a via opening through said upper hard mask layer and said lower hard mask layer to a top surface of said dielectric stack;

using a second reactive ion etch selective to said upper hard mask layer and said interlevel dielectric layer over said dielectric barrier layer, extending said via opening through said interlevel dielectric layer to said dielectric barrier layer;

removing said lower hard mask layer using a wet etch;

using a third reactive ion etch selective to said interlevel dielectric layer over said dielectric barrier layer, etching a trench part way through said interlevel dielectric layer, said via opening exposed in a bottom of said trench;

using a fourth reactive ion etch selective to said dielectric barrier layer over said damascene conductor and said interlevel dielectric layer to said damascene conductor, extending said via opening through said dielectric barrier layer to said damascene conductor; and

filling said trench and via opening with an electrical conductor.

12. The method of claim 11 , wherein said upper hard mask layer comprise a metal nitride and said lower hard mask layer comprises a metal oxide or metal oxynitride.

13. The method of claim 11 , wherein said upper hard mask layer comprise titanium nitride and said lower hard mask layer comprises a titanium oxide or titanium oxynitride, said damascene conductor comprises tungsten or copper and said interlevel dielectric layer comprises an ultra low K material have a dielectric constant of 2.7 or less.

14. The method of claim 11 , wherein said wet etch comprises an aqueous solution of hydrogen fluoride and citric acid.

15. The method of claim 11 , further including:

between performing said wet etch and performing said third reactive ion etch forming a second patterned photoresist layer on a top surface of interlevel dielectric layer, an opening in said second patterned hard mask layer defining a perimeter of said trench and after said third reactive ion etch, removing said second patterned hard mask layer; and

between said forming said upper hard mask layer and performing said first reactive ion etch forming a patterned photoresist layer on a top surface of upper hard mask layer, an opening in said patterned hard mask layer defining a perimeter of said via opening and removing said patterned hard mask layer using said second reactive ion etch; or

between said forming said upper hard mask layer and performing said first reactive ion etch, forming an additional hardmask layer on a top surface of said upper hardmask layer, forming a patterned photoresist layer on a top surface of additional hard mask layer, using said patterned photoresist layer forming an opening in said additional hardmask layer using an additional reactive ion etch, removing said patterned photoresist layer, said opening in said additional hardmask layer defining a perimeter of said via opening, said first reactive ion etch selective to said upper and lower hardmask layers over said additional hardmask layer, said second reactive ion etch removing said additional hardmask layer.

16. The method of claim 11 wherein:

said interlevel dielectric layer includes a dielectric capping layer on a top surface of said interlevel dielectric layer and said lower hard mask layer is formed on a top surface of said dielectric capping layer;

said first reactive ion etch is also selective to said upper and lower hard mask layers over said dielectric capping layer and extends said opening to said dielectric capping layer;

said second reactive ion etch is also selective to said dielectric capping layer over said dielectric barrier layer and extends said opening through said dielectric capping layer

said third reactive ion etch is also selective to said dielectric capping layer over said dielectric barrier layer and extends said trench through said dielectric capping layer;

said fourth reactive ion etch is also selective to said dielectric barrier layer over said dielectric capping layer.

17. The method of claim 16 , wherein said upper hard mask layer comprise a metal nitride and said lower hard mask layer comprises a metal oxide or metal oxynitride.

18. The method of claim 16 , wherein said upper hard mask layer comprise titanium nitride and said lower hard mask layer comprises a titanium oxide or titanium oxynitride, said damascene conductor comprises tungsten or copper and said interlevel dielectric layer comprises an ultra low K material have a dielectric constant of 2.7 or less.

19. The method of claim 16 , wherein said wet etch comprises an aqueous solution of hydrogen fluoride and citric acid between 22° C. and 70° C.

20. The method of claim 16 , further including:

between performing said wet etch and performing said third reactive ion etch forming a second patterned photoresist layer on a top surface of interlevel dielectric layer, an opening in said second patterned hard mask layer defining a perimeter of said trench and after said third reactive ion etch, removing said second patterned hard mask layer; and

between said forming said upper hard mask layer and performing said first reactive ion etch forming a patterned photoresist layer on a top surface of upper hard mask layer, an opening in said patterned hard mask layer defining a perimeter of said via opening and removing said patterned hard mask layer using said second reactive ion etch; or

between said forming said upper hard mask layer and performing said first reactive ion etch, forming an additional hardmask layer on a top surface of said upper hardmask layer, forming a patterned photoresist layer on a top surface of additional hard mask layer, using said patterned photoresist layer forming an opening in said additional hardmask layer using an additional reactive ion etch, removing said patterned photoresist layer, said opening in said additional hardmask layer defining a perimeter of said via opening, said first reactive ion etch selective to said upper and lower hardmask layers over said additional hardmask layer, said second reactive ion etch removing said additional hardmask layer.

21. A method, comprising:

providing a substrate having a dielectric barrier layer over an underlying conductor;

forming a dielectric stack on said substrate;

forming a lower hard mask layer comprising a metal and oxygen on a top surface of said dielectric stack and forming an upper hard mask layer on a top surface of said lower hard mask layer;

forming an opening through said upper hard mask layer and said lower hardmask layer;

extending said opening through said dielectric layer to said dielectric barrier layer;

removing said lower hard mask layer using a wet etch;

extending said opening through said dielectric barrier layer to said underlying conductor; and

filling said opening with an electrical conductor.