Pseudo butted junction structure for back plane connection
View Patent ↗Butted p-n junctions interconnecting back gates in an SOI process, methods for making butted p-n junctions, and design structures. The butted junction includes an overlapping region formed in the bulk substrate by overlapping the mask windows of the ion-implantation masks used to form the back gates. A damaged region may be selectively formed to introduce mid-gap energy levels in the semiconductor material of the overlapping region employing one of the implantation masks used to form the back gates. The damage region causes the butted junction to be leaky and conductively couples the overlapped back gates to each other and to the substrate. Other back gates may be formed that are floating and not coupled to the substrate.
1. A device structure formed on a semiconductor-on-insulator (SOI) substrate having a semiconductor layer, a bulk substrate of a first conductivity type, and buried dielectric layer between the semiconductor layer and the bulk substrate, the device structure comprising:
a first back gate of the first conductivity type in the bulk substrate, the first back gate electrically coupled with the bulk substrate of the first conductivity type;
a second back gate of a second conductivity type in the bulk substrate, the second back gate laterally adjacent to the first back gate;
an overlapping region defined by spatial coincidence of a portion of the first back gate and a portion of the second back gate, the overlapping region configured to electrically couple the second back gate with the first back gate so that the second back gate is electrically coupled with the bulk substrate; and
a damage region extending laterally across the overlapping region from the first back gate to the second back gate, the damage region cooperating with the overlapping region to provide a leakage current electrically coupling the second back gate with the first back gate.
2. The device structure of claim 1 wherein the damage region includes defects in a crystalline lattice structure of the bulk substrate that that supply midgap energy levels in a bandgap of the semiconductor material of the bulk substrate.
3. The device structure of claim 1 wherein the damage region includes a concentration of a dopant that supplies midgap energy levels in a bandgap of the semiconductor material of the bulk substrate.
4. The device structure of claim 1 further comprising:
a third back gate of the second conductivity type in the substrate, the third back gate electrically isolated from the first back gate, the second back gate, and the substrate.
5. The device structure of claim 1 further comprising:
a first transistor including a gate stack over the first back gate and separated from the first back gate by the buried dielectric layer; and
a second transistor including a gate stack over the second back gate and separated from the second back gate by the buried dielectric layer.
6. The device structure of claim 5 wherein the first and second transistors have different threshold voltages, and the first and second back gates are configured to receive a first back-gate voltage to modulate the respective threshold voltages of the first and second transistors.
7. The device structure of claim 1 wherein the semiconductor layer has a thickness of 30 nm or less, and the buried dielectric layer has a thickness of 20 nm or less.
8. The device structure of claim 7 further comprising:
a third back gate of the second conductivity type formed in the substrate, the third back gate electrically isolated from the first back gate, the second back gate, and the substrate; and
a third transistor including a gate stack over the third back gate and separated from the third back gate by the buried dielectric layer,
wherein the third back gate is configured to receive a second back-gate voltage to modulate a threshold voltage of the third transistor.