Resistance variable memory cell structures and methods
Resistance variable memory cell structures and methods are described herein. A number of embodiments include a first resistance variable memory cell comprising a number of resistance variable materials in a super-lattice structure and a second resistance variable memory cell comprising the number of resistance variable materials in a homogeneous structure.
1. An array of resistance variable memory cells, comprising:
a first resistance variable memory cell comprising a number of resistance variable materials in a super-lattice structure; and
a second resistance variable memory cell comprising the number of resistance variable materials in a homogeneous structure.
2. The array of claim 1 , wherein the number of resistance variable materials include phase change materials.
3. The array of claim 1 , wherein the number of resistance variable materials in the super-lattice structure include portions of each of the number of resistance variable materials stacked upon each other to form the super-lattice structure.
4. The array of claim 1 , wherein the super-lattice structure is a storage element of the first resistance variable memory cell and the homogeneous structure is a storage element of the second resistance variable memory cell.
5. The array of claim 1 , wherein the super-lattice structure is a select device of the first resistance variable memory cell and the homogeneous structure is a select device of the second resistance variable memory cell.
6. The array of claim 1 , wherein the number of resistance variable materials in the homogeneous structure are ion implanted resistance variable materials.
7. The array of claim 1 , wherein the first resistance variable memory cell is located in a first portion of the array configured to store a first type of data and the second resistance variable memory cell is located in a second portion of the array configured to store a second type of data.
8. An array of resistance variable memory cells, comprising:
a first number of resistance variable memory cells in a first portion of the array, wherein the first number of resistance variable memory cells each include a number of resistance variable materials having a super-lattice structure; and
a second number of resistance variable memory cells in a second portion of the array, wherein the second number of resistance variable memory cells each include the number of resistance variable materials having a homogeneous structure.
9. The array of claim 8 , wherein the first portion of the array is configured to store a first type of data, and the second portion of the array is configured to store a second type of data.
10. The array of claim 8 , wherein the second number of resistance variable memory cells have a higher associated retention capability than the first number of resistance variable memory cells.
11. The array of claim 8 , wherein the first number of resistance variable memory cells have a higher associated programming throughput than the second number of resistance variable memory cells.
12. The array of claim 8 , wherein the array is configured to store dynamic data in the first number of resistance variable memory cells and static data in the second number of resistance variable memory cells.