Broadband amplifier topology with current shutdown

1. An apparatus comprising:

a first depletion-mode transistor having a common source configuration;

a first enhancement-mode transistor having a common gate configuration, wherein said first depletion-mode transistor and said first enhancement-mode transistor are coupled in a cascade arrangement and a gate of said first enhancement-mode transistor is biased in response to a potential at a drain of said first enhancement-mode transistor; and

a pull down switch operatively coupled between said gate of said first enhancement-mode transistor and a circuit ground.

2. The apparatus according to claim 1 , wherein said pull down switch comprises a second enhancement-mode transistor having a source connected to said circuit ground and a drain connected to the gate of said first enhancement-mode transistor.

3. The apparatus according to claim 2 , wherein said pull down switch further comprises:

a second depletion-mode transistor; and

a third enhancement-mode transistor, said third enhancement-mode transistor having a common source configuration and coupled with said second depletion-mode transistor to form an inverter, wherein an output of said inverter is coupled to a gate of said second enhancement-mode transistor.

4. The apparatus according to claim 1 , wherein said apparatus is part of a broadband radio frequency (RF) amplifier.

5. The apparatus according to claim 4 , wherein said pull down switch implements a current shutdown of said broadband RF amplifier.

6. The apparatus according to claim 1 , wherein said first depletion-mode transistor and said first enhancement-mode transistor comprise field effect transistors (FETs).

7. The apparatus according to claim 1 , wherein each of said first depletion-mode transistor and said first enhancement-mode transistor comprise a psuedomorphic high electron mobility transistor (pHEMT).

8. The apparatus according to claim 1 , wherein said first depletion-mode transistor, said first enhancement-mode transistor, and said pull down switch are fabricated on a monolithic microwave integrated circuit (MMIC).

9. The apparatus according to claim 1 , further comprising:

a bias circuit configured to bias said gate of said first enhancement-mode transistor in response to said potential at said drain of said first enhancement-mode transistor.

10. The apparatus according to claim 1 , further comprising:

a passive potential divider circuit coupled to said drain and said gate of said first enhancement-mode transistor.

11. A method of implementing a broadband amplifier with current shutdown comprising:

coupling a first depletion-mode transistor having a common source configuration to a first enhancement-mode transistor having a common gate configuration, wherein said first depletion-mode transistor and said first enhancement-mode transistor are coupled in a cascode arrangement and a gate of said first enhancement-mode transistor is biased in response to a potential at a drain of said first enhancement-mode transistor; and

coupling a pull down switch between a gate of said first enhancement-mode transistor and a circuit ground.

12. The method according to claim 11 , wherein said pull down switch comprises a second enhancement-mode transistor having a source connected to said circuit ground and a drain connected to the gate of said first enhancement-mode transistor.

13. The method according to claim 12 , wherein said pull down switch further comprises:

a second depletion-mode transistor; and

a third enhancement-mode transistor, said third enhancement-mode transistor having a common source configuration and coupled with said second depletion-mode transistor to form an inverter, wherein an output of said inverter is coupled to a gate of said second enhancement-mode transistor.

14. The method according to claim 11 , wherein said broadband amplifier comprises a radio frequency (RF) amplifier.

15. The method according to claim 14 , wherein said pull down switch implements a current shutdown of said broadband RF amplifier.

16. The method according to claim 11 , wherein said first depletion-mode transistor and said first enhancement-mode transistor are fabricated as part of a monolithic microwave integrated circuit (MMIC) using a psuedomorphic high electron mobility transistor (pHEMT) process.

17. The method according to claim 11 , further comprising:

coupling a passive potential divider circuit to said drain and said gate of said first enhancement-mode transistor.

18. An apparatus comprising:

a first depletion-mode transistor having a common source configuration;

a first enhancement-mode transistor having a common gate configuration, wherein said first depletion-mode transistor and said first enhancement-mode transistor are coupled in a cascode arrangement;

a second enhancement-mode transistor having a source connected to a circuit ground and a drain connected to a gate of said first enhancement-mode transistor; and

a third enhancement-mode transistor having a common source configuration and coupled with a second depletion-mode transistor to form an inverter, wherein an output of said inverter is coupled to a gate of said second enhancement-mode transistor.

19. The apparatus according to claim 18 , wherein said apparatus is fabricated as an integrated circuit.

20. The apparatus according to claim 18 , wherein each of said first depletion-mode transistor, said first enhancement-mode transistor, said second enhancement-mode transistor, and said third enhancement-mode transistor comprise a psuedomorphic high electron mobility transistor (pHEMT) and are fabricated on a monolithic microwave integrated circuit (MMIC).