Imaging systems with switchable column power control
View Patent ↗Electronic devices may include image sensors having image pixel arrays with image pixels arranged in pixel rows and pixel columns. Each pixel column may be coupled to a column line having column readout circuitry and column power control circuitry that selectively enables or disables the column readout circuitry for various column lines. The column power control circuitry and the column readout circuitry may be coupled to column decoder circuitry. The column decoder circuitry may provide a column address signals to the power control and the readout circuitry. The power control circuitry may enable only column lines for which column addresses have been received.
1. An image sensor, comprising:
an array of image pixels arranged in pixel rows and pixel columns;
a plurality of column lines, wherein each one of the plurality of column lines is coupled to a corresponding pixel column;
column readout circuitry including analog-to-digital conversion circuitry and memory, wherein each one of the plurality of column lines is coupled to the column readout circuitry; and
column power control circuitry having at least one flip-flop with an input terminal configured to receive a power update clock signal, wherein the column power control circuitry is configured to selectively power on and power off the analog-to-digital conversion circuitry and the memory based on received column addresses and wherein the received column addresses indicate which portions of the analog-to-digital conversion circuitry and the memory are powered on and which portions of the analog-to-digital conversion circuitry and the memory are powered off.
2. The image sensor defined in claim 1 wherein the column power control circuitry further comprises a set-reset latch coupled to the at least one flip-flop.
3. The image sensor defined in claim 2 wherein the column power control circuitry further comprises an OR gate coupled to the set-reset latch.
4. The image sensor defined in claim 3 wherein the OR gate is coupled to a set input of the set-reset latch.
5. The image sensor defined in claim 4 wherein the column power control circuitry further comprises an NOR gate coupled to the at least one flip-flop.
6. The image sensor defined in claim 5 wherein the column control circuitry further comprises an additional OR gate coupled to the NOR gate.
7. The image sensor defined in claim 6 wherein the flip-flop comprises an output terminal and wherein the output terminal of the flip-flop is connected to an input terminal of the NOR gate.
8. The image sensor defined in claim 7 wherein the NOR gate comprises an output terminal and wherein the output terminal of the NOR gate is connected to an input terminal of the additional OR gate.
9. The image sensor defined in claim 8 wherein the column readout circuitry comprises:
multiplexing circuitry.
10. The image sensor defined in claim 1 , wherein the column power control circuitry is configured to alternately power on and power off alternating columns of the analog-to-digital conversion circuitry and the memory in a horizontal skip mode.
11. An image sensor, comprising:
an array of image pixels arranged in pixel rows and pixel columns;
a plurality of column lines, wherein each one of the plurality of column lines is coupled to a corresponding pixel column;
column readout circuitry, wherein each one of the plurality of column lines is coupled to the column readout circuitry; and
column power control circuitry having a flip-flop, a latch coupled to an input terminal of the flip-flop, an OR gate coupled to the latch, a NOR gate coupled to an output terminal of the flip-flop, and an additional OR gate that receives an output from the NOR gate and a horizontal skip mode signal, wherein the column power control circuitry is configured to alternately power on and power off alternating columns of the column readout circuitry in a horizontal skip mode when the horizontal skip mode signal is asserted.
12. The image sensor defined in claim 11 , further comprising:
additional column circuitry, wherein the column power control circuitry is configured to receive column addresses from the additional column circuitry.
13. The image sensor defined in claim 12 wherein the column readout circuitry comprises analog-to-digital conversion circuitry coupled to each of the plurality of column lines.
14. The image sensor defined in claim 13 wherein the column readout circuitry further comprises amplifiers coupled to each of the plurality of column lines.
15. The image sensor defined in claim 14 wherein the column readout circuitry further comprises memory for storing pixel signals from the array of image pixels.
16. The image sensor defined in claim 15 wherein the column readout circuitry further comprises multiplexing and demultiplexing circuitry coupled to the plurality of column lines.
17. The image sensor defined in claim 16 , further comprising row control circuitry configured to provide row control signals to the pixel rows.
18. A system, comprising:
a central processing unit;
input-output circuitry; and
an imaging device, wherein the imaging device comprises:
an array of image pixels arranged in pixel rows and pixel columns;
a plurality of column lines, wherein each one of the plurality of column lines is coupled to a corresponding pixel column;
column readout circuitry including analog-to-digital conversion circuitry and memory, wherein each one of the plurality of column lines is coupled to the column readout circuitry;
column power control circuitry having at least one flip-flop with an input terminal configured to receive a power update clock signal, wherein the column power control circuitry is configured to selectively power-on and power-off the column readout circuitry based on column addresses and wherein the column addresses indicate which portions of the analog-to-digital conversion circuitry and the memory are powered on and which portions of the analog-to-digital conversion circuitry and the memory are powered off; and
processing circuitry, wherein the column power control circuitry receives the column addresses from the processing circuitry.
19. The system defined in claim 18 wherein the column power control circuitry further comprises a latch and an OR gate coupled to an additional input terminal of the at least one flip-flop and a NOR gate and an additional OR gate coupled to an output terminal of the at least one flip-flop.