IP Library Granted Patent US 9,024,203
Granted Patent B2
US 9,024,203 · App. 13/928,701 · Granted May 5, 2015

Embedded printed circuit board and method for manufacturing same

Inventor: Chien-Kuang Lai (Taoyuan, TW)
Assignee: Zhen Ding Technology Co., Ltd.
H05K1/184H05K1/183H05K1/186H05K3/323H05K3/4602H05K3/4652H05K2201/0397H05K2201/10636Y10T29/49162
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Quick Facts
Patent No.
US 9,024,203
App. No.
13/928,701
Granted
May 5, 2015
Kind
B2
Abstract

A method for manufacturing an embedded printed circuit board includes the following steps. First, a circuit substrate is provided. The circuit substrate includes a base, a first wiring layer, and a second wiring layer. The first wiring layer includes a number of electrode connection wires. Second, an opening is defined in the circuit substrate. The opening passes through the base and the second wiring layer. Third, an anisotropic conductive film is adhered onto the electrode connection wires in the opening. Fourth, an electrical element including many electrodes is provided. Fifth, the electrical element is arranged in the opening, with the electrodes respectively spatially correspond to the electrode connection wires, and each electrode is electrically connected to the corresponding electrode connection wire through the anisotropic conductive film, thereby obtaining an embedded printed circuit board.

Claims (21)

1. An embedded printed circuit board, comprising:

a circuit substrate, the circuit substrate comprising a base, a first wiring layer, and a second wiring layer, the first wiring layer and the second wiring layer being respectively arranged at opposite surfaces of the base, the first wiring layer comprising a plurality of electrode connection wires, the circuit substrate defining an opening, the opening being spatially corresponding to the electrode connection wires, thereby exposing the electrode connection wires;

an anisotropic conductive film received in the opening and adhered on the electrode connection wires; and

an electrical element arranged in the opening of the circuit substrate, the electrical element comprising a plurality of electrodes, the electrodes respectively corresponding to the electrode connection wires, and each electrode being electrically connected to the corresponding electrode connection wire through the anisotropic conductive film.

2. The embedded printed circuit board of claim 1 , further comprising a first adhesive sheet, a second adhesive sheet, a third wiring layer, and a fourth wiring layer, the first adhesive sheet being laminated on the second wiring layer, the second adhesive sheet being laminated on the first wiring layer, the third wiring layer being formed at a side of the first adhesive sheet further away from the second wiring layer, the fourth wiring layer being formed at a side of the second adhesive sheet further away from the first wiring layer, the third wiring layer being electrically connected to the second wiring layer through a conductive via in the first adhesive sheet, and the fourth wiring layer being electrically connected to the first wiring layer through a conductive via in the second adhesive sheet.

3. The embedded printed circuit board of claim 1 , further comprising a first solder mask and a second solder mask, the first solder mask being formed on first the third wiring layer and in gaps defined in the third wiring layer, and defining a plurality of openings in the first solder mask, thereby enabling portions of the third wiring layer exposed from the openings in the first solder mask to serve as contact pads, the second solder mask being formed on the fourth wiring layer and in gaps defined in the fourth wiring layer, defining a plurality of openings in the second solder mask, thereby enabling portions of the fourth wiring layer exposed from the openings in the second solder mask to serve as solder pads.

4. The embedded printed circuit board of claim 1 , wherein the base is an insulating resin layer, and the first wiring layer is electrically connected to the second wiring layer through a conductive via in the base.

5. The embedded printed circuit board of claim 1 , the electrode connection wires are two electrode connection wires adjacent to and separated from each other, and the electrodes are two electrodes respectively corresponding to the two electrode connection wires.

6. A method for manufacturing an embedded printed circuit board, comprising:

providing a circuit substrate, the circuit substrate comprising a base, a first wiring layer, and a second wiring layer, the first wiring layer and the second wiring layer being respectively arranged at opposite surfaces of the base, the first wiring layer comprising a plurality of electrode connection wires;

defining an opening in the circuit substrate at a position spatially corresponding to the electrode connection wires, the opening passing through the base and the second wiring layer;

arranging an anisotropic conductive film in the opening and adhering the anisotropic conductive film onto the electrode connection wires;

providing an electrical element, the electrical element comprising a plurality of electrodes;

arranging the electrical element in the opening, with the electrodes respectively spatially correspond to the electrode connection wires, and each electrode electrically connected to the corresponding electrode connection wire through the anisotropic conductive film, thereby obtaining an embedded printed circuit board.

7. The method of claim 6 , wherein after arranging the electrical element in the opening, the method further comprises:

laminating a first adhesive sheet and a first copper layer onto the second wiring layer, such that the first adhesive sheet is sandwiched between the first copper layer and the second wiring layer, and laminating a second adhesive sheet and a second copper layer onto the first wiring layer, such that second adhesive sheet is sandwiched between the second copper layer and the first wiring layer; and

patterning the first copper layer into a third wiring layer, patterning the second copper layer into a fourth wiring layer, electrically connecting the first wiring layer and the fourth wiring layer, and electrically connecting the second wiring layer and the third wiring layer.

8. The method of claim 7 , wherein after patterning the first copper layer into a third wiring layer, patterning the second copper layer into a fourth wiring layer, electrically connecting the first wiring layer and the fourth wiring layer, and electrically connecting the second wiring layer and the third wiring layer, the method further comprises:

forming a first solder mask on the third wiring layer and in gaps defined in the third wiring layer, defining a plurality of openings in the first solder mask, thereby enabling portions of the third wiring layer exposed from the openings in the first solder mask to serve as contact pads, and forming a second solder mask on the fourth wiring layer and in gaps defined in the fourth wiring layer, defining a plurality of openings in the second solder mask, thereby enabling portions of the fourth wiring layer exposed from the openings in the second solder mask to serve as solder pads.

9. The method of claim 6 , wherein the opening in the circuit substrate is defined by laser ablation.

10. The method of claim 6 , wherein the electrode connection wires are two electrode connection wires adjacent to and separated from each other.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2023
From: QI DING TECHNOLOGY QINHUANGDAO CO., LTD.; ZHEN DING TECHNOLOGY CO., LTD.
To: LEADING INTERCONNECT SEMICONDUCTOR TECHNOLOGY QINHUANGDAO CO., LTD.; ZHEN DING TECHNOLOGY CO., LTD.
Reel/Frame 064899/0050 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2016
From: ZHEN DING TECHNOLOGY CO., LTD.
To: QI DING TECHNOLOGY QINHUANGDAO CO., LTD.; ZHEN DING TECHNOLOGY CO., LTD.
Reel/Frame 039806/0499 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 27, 2013
From: LAI, CHIEN-KUANG
To: ZHEN DING TECHNOLOGY CO., LTD.
Reel/Frame 030702/0063 →
Priority Claims (1)
CN 2012 1 04322999 · Nov 2, 2012 · national
Continuity (1)
Related Publication 20140124245A1 · May 8, 2014