IP Library › Patent Application 13938749
Patent Application
App. No. 13/938,749

METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER, AND SEMICONDUCTOR WAFER

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Quick Facts
Patent No.
US None
App. No.
13/938,749
Abstract

A method for manufacturing a semiconductor wafer includes the steps of forming, on a first principal surface of a substrate, a compound semiconductor layer different in kind from the substrate, and removing, by etching, a part of the compound semiconductor layer. The part of the compound semiconductor layer is formed on an outer peripheral portion of the first principal surface of the substrate.

Claims (26)

1 . A method for manufacturing a semiconductor wafer, comprising the steps of:

(a) forming, on a first principal surface of a substrate, a compound semiconductor layer different in kind from the substrate; and

(b) removing, by etching, a part of the compound semiconductor layer, the part of the compound semiconductor layer being formed on an outer peripheral portion of the first principal surface of the substrate.

2 . The method according to claim 1 , further comprising the step of:

(c) performing a plurality of processes to form semiconductor devices in the compound semiconductor layer, wherein

step (b) is performed while performing any one of the plurality of processes.

3 . The method according to claim 2 , wherein step (b) is performed while isolating the semiconductor devices.

4 . The method according to claim 1 , wherein the substrate is a silicon substrate.

5 . The method according to claim 1 , wherein the compound semiconductor layer contains a nitride-based compound semiconductor.

6 . The method according to claim 1 , further comprising the step of:

(d) reducing thickness of the substrate by polishing or grinding a second principal surface of the substrate that is different from the first principal surface on which the compound semiconductor layer is formed.

7 . The method according to claim 6 , further comprising the step of:

(e) dividing the semiconductor wafer into a plurality of chips after step (d).

8 . A method for manufacturing a semiconductor wafer, comprising the step of:

(a) forming, on a first principal surface of a substrate, a compound semiconductor layer different in kind from the substrate, wherein

in step (a), the compound semiconductor layer is formed while masking an outer peripheral portion of the first principal surface of the substrate.

9 . The method according to claim 8 , wherein the substrate is a silicon substrate.

10 . The method according to claim 8 , wherein the compound semiconductor layer contains a nitride-based compound semiconductor.

11 . The method according to claim 8 , further comprising the step of:

(d) reducing thickness of the substrate by polishing or grinding a second principal surface of the substrate that is different from the first principal surface on which the compound semiconductor layer is formed.

12 . The method according to claim 11 , further comprising the step of:

(e) dividing the semiconductor wafer into a plurality of chips after step (d).

13 . A semiconductor wafer comprising:

a substrate; and

a compound semiconductor layer formed on a principal surface of the substrate, the compound semiconductor layer being different in kind from the substrate, wherein

on an outer peripheral portion of the principal surface of the substrate, a region where the compound semiconductor layer is partially removed by etching is formed.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2014
From: ADVANCED POWER DEVICE RESEARCH ASSOCIATION
To: FURUKAWA ELECTRIC CO., LTD.; FUJI ELECTRIC CO., LTD.
Reel/Frame 032202/0112 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2013
From: MAKINO, RYOHEI; KUMADA, TAKAO; EDO, MASAHARU; TAKAKI, KEISHI
To: ADVANCED POWER DEVICE RESEARCH ASSOCIATION
Reel/Frame 030770/0685 →