MOSFET with thin semiconductor channel and embedded stressor with enhanced junction isolation and method of fabrication
A field effect transistor structure that uses thin semiconductor on insulator channel to control the electrostatic integrity of the device. Embedded stressors are epitaxially grown in the source/drain area from a template in the silicon substrate through an opening made in the buried oxide in the source/drain region. In addition, a dielectric layer is formed between the embedded stressor and the semiconductor region under the buried oxide layer, which is located directly beneath the channel to suppress junction capacitance and leakage.
1. A method of fabricating a semiconductor structure, comprising:
providing a semiconductor substrate;
forming a buried oxide layer having a thickness of from 10 to 50 nm within the semiconductor substrate;
forming a gate structure on the semiconductor substrate;
defining a channel region having a thickness of from 5 to 10 nm between the gate structure and the buried oxide layer;
forming a recess adjacent to the gate structure,
wherein the recess extends through the buried oxide layer into the semiconductor substrate;
forming a dielectric layer at a sidewall of the recess,
wherein the dielectric layer at least partially covers a side of the buried oxide layer;
epitaxially growing a first region within the recess wherein the first region has a lattice constant different from the lattice constant of the semiconductor substrate; and
epitaxially growing a second region on the first region:
wherein the first region is undoped or has a dopant concentration of less than 1·10 18 atoms/cm 3 and the second region has a dopant concentration of more than 1·10 19 atoms/cm 3 .
2. The method of claim 1 , wherein the forming the recess comprises dry etching.
3. The method of claim 1 , wherein the recess has a depth of from 50 to 200 nm.
4. The method of claim 1 , wherein the second epitaxially-grown region exerts a uniaxial tensil or compressive stress onto the channel region.
5. The method of claim 1 , wherein at least one of the forming the first epitaxially-grown region or the forming the second epitaxially-grown region comprises in-situ doping.
6. The method of claim 1 , wherein the forming the dielectric layer comprises pulling down an intermediate height of the dielectric layer to a final height.
7. The method of claim 1 , wherein the second epitaxially-grown region comprises Silicon Germanium (SiGe).
8. The method of claim 7 , wherein an amount of Germanium in the SiGe is of from 20 to 70%.
9. The method of claim 1 , wherein the second epitaxially-grown region comprises Silicon Carbide (SiC).
10. The method of claim 9 , wherein an amount of carbon in the silicon carbide is of from 0.5 to 5%.
11. The semiconductor structure of claim 10 , wherein the amount of carbon is of from 1.5 to 2%.
12. The method of claim 1 , wherein the second epitaxially-grown region exerts a tensile or compressive stress upon the channel region.
13. The method of claim 1 , wherein the first epitaxially-grown region comprises a first dopant and the second epitaxially-grown region comprises a second dopant and wherein the first dopant and the second dopant have an opposite polarity.
14. The method of claim 1 , wherein the semiconductor substrate further comprises a second buried oxide layer under the first epitaxially-grown region.
15. The method of claim 1 , which does not contain any raised source and drain regions.
16. The method of claim 1 , which comprises providing raised source and drain regions that are minimized to thereby reduce parasitic capacitance.
17. The method of claim 1 , wherein the gate has a thickness of 20 nm to 50 nm.
18. The method of claim 1 , wherein the recess has a depth as measured from the top of the semiconductor substrate to the bottom of the recess of 70 to 100 nm.
19. The method of claim 1 , wherein the second epitaxially-grown region comprises the same semiconductor material as the first epitaxially-grown region.