Pillar-shaped nonvolatile memory and method of fabrication
View Patent ↗A pillar-shaped memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. Other aspects are also provided.
1. A pillar-shaped memory cell comprising:
an input terminal and an output terminal;
a steering element; and
a non-volatile state change element coupled in series with the steering element,
wherein the steering element and state change element comprise a pillar coupled between the input terminal and the output terminal.
2. The pillar-shaped memory cell of claim 1 , wherein the steering element comprises a p-n diode, a p-i-n diode or a Schottky diode.
3. The pillar-shaped memory cell of claim 1 , wherein the state change element comprises a reversible resistance-switching element.
4. The pillar-shaped memory cell of claim 1 , wherein the state change element is capable of having more than two resistance states.
5. The pillar-shaped memory cell of claim 1 , wherein the state change element is rewriteable.
6. The pillar-shaped memory cell of claim 1 , wherein the state change element comprises a multi-state antifuse.
7. A three-dimensional memory array including:
a first memory level comprising a first plurality of the pillar-shaped memory cells of claim 1 ; and
a second memory level disposed vertically above the first memory level, the second memory level comprising a second plurality of the pillar-shaped memory cells of claim 1 .
8. A method of forming a pillar-shaped memory cell, the method comprising:
forming a steering element; and
forming a non-volatile state change element in series with the steering element,
wherein the steering element and state change element comprise a pillar coupled between an input terminal and an output terminal of the memory cell.
9. The method of claim 8 , wherein the steering element comprises a p-n diode, a p-i-n diode or a Schottky diode.
10. The method of claim 8 , wherein the state change element comprises a reversible resistance-switching element.
11. The method of claim 8 , wherein the state change element is capable of having more than two resistance states.
12. The method of claim 8 , wherein the state change element is rewriteable.
13. The method of claim 8 , wherein the state change element comprises a multi-state antifuse.
14. A method of forming a three-dimensional memory array, the method comprising:
forming a first memory level comprising a first plurality of the pillar-shaped memory cells formed according to the method of claim 8 ; and
forming a second memory level vertically above the first memory level, the second memory level comprising a second plurality of the pillar-shaped memory cells formed according to the method of claim 8 .
15. A memory cell comprising:
a steering element; and
a non-volatile state change element coupled in series with the steering element,
wherein the steering element and the state change element are vertically stacked.
16. The memory cell of claim 15 , wherein the steering element comprises a p-n diode, a p-i-n diode or a Schottky diode.
17. The memory cell of claim 15 , wherein the state change element comprises a reversible resistance-switching element.
18. The memory cell of claim 15 , wherein the state change element is capable of having more than two resistance states.
19. The memory cell of claim 15 , wherein the state change element is rewriteable.
20. The memory cell of claim 15 , wherein the state change element comprises a multi-state antifuse.
21. A three-dimensional memory array including:
a first memory level comprising a first plurality of the memory cells of claim 15 ; and
a second memory level disposed vertically above the first memory level, the second memory level comprising a second plurality of the memory cells of claim 15 .