RF LDMOS device and fabrication method thereof
A radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) device is disclosed, wherein a lightly doped n-type drain region has a laterally non-uniform n-type dopant concentration distribution, which is achieved by forming a moderately n-type doped region, having a higher doping concentration and a greater depth than the rest portion of the lightly doped n-type drain region, in a portion of the lightly n-type doped region proximate to the polysilicon gate. The structure enables the RF LDMOS device of the present invention to have both a high breakdown voltage and a significantly reduced on-resistance. A method of fabricating such a RF LDMOS device is also disclosed.
1. A method of fabricating a radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) device, comprising the steps of:
providing a substrate;
forming a p-type epitaxial layer over the substrate;
forming a p-type well in a first portion of the p-type epitaxial layer;
forming a lightly doped n-type drain region in a second portion of the p-type epitaxial layer, the lightly doped n-type drain region being separated from the p-type well;
forming a moderately doped n-type region in a first portion of the lightly doped n-type drain region, the moderately doped n-type region having a depth greater than a depth of the lightly doped n-type drain region;
forming a heavily doped n-type drain region in a second portion of the lightly doped n-type drain region, the heavily doped n-type drain region being separated from the moderately doped n-type region; and
forming a heavily doped n-type source region in an upper portion of the p-type well,
wherein an n-type dopant concentration of the moderately doped n-type region is lower than both n-type dopant concentrations of the heavily doped n-type drain region and the heavily doped n-type source region and is higher than or equal to an n-type dopant concentration of the lightly doped n-type drain region.
2. The method according to claim 1 , comprising the following steps in the sequence set forth:
1) growing a p-type epitaxial layer over a p-type substrate;
2) forming a p-type well in the p-type epitaxial layer;
3) forming a gate oxide layer, a polysilicon gate, a lightly doped n-type drain region and a lightly doped n-type source region, the gate oxide layer covering a portion of the p-type well and a portion of the p-type epitaxial layer, the polysilicon gate covering the gate oxide layer, the lightly doped n-type source region being formed at least in a portion of the p-type well on a first side of the gate oxide layer, the lightly doped n-type drain region being formed in a portion of the p-type epitaxial layer on a second side of the gate oxide layer;
4) forming a moderately doped n-type region in a first portion of the lightly doped n-type drain region, the moderately doped n-type region having a depth greater than a depth of the lightly doped n-type drain region;
5) forming a heavily doped p-type region, a heavily doped n-type source region and a heavily doped n-type drain region, the heavily doped p-type region being formed in a first portion of the lightly doped n-type source region, the heavily doped n-type source region being formed in a second portion of the lightly doped n-type source region, the heavily doped n-type drain region being formed in a second portion of the lightly doped n-type drain region; and
6) forming an oxide layer, at least one Faraday shield and a contact column.
3. The method according to claim 2 , wherein in the step 2), the p-type well is formed in the p-type epitaxial layer by implanting p-type dopant ions followed by high temperature drive-in.
4. The method according to claim 3 , wherein the p-type dopant ions are boron ions and are implanted at a dose of 1E12 to 1E14 atoms/cm 2 and an energy of 30 KeV to 80 KeV, and wherein the high temperature drive-in is performed at a temperature of 800° C. to 1200° C.
5. The method according to claim 2 , wherein the moderately doped n-type region has a length of 0 μm to 4 μm, wherein a distance between the moderately doped n-type region and the polysilicon gate is greater than or equal to 0.1 μm, and wherein the depth of the moderately doped n-type region is 0.1 μm to 0.5 μm greater than the depth of the lightly doped n-type drain region.
6. The method according to claim 2 , wherein in the step 4), the lightly doped n-type drain region is formed by implanting n-type phosphorus or arsenic ions at a dose of 5E11 to 4E12 atoms/cm 2 and an energy of 100 KeV to 300 KeV.
7. The method according to claim 2 , wherein in the step 5), both the heavily doped n-type source region and the heavily doped n-type drain region are formed by implanting n-type phosphorus or arsenic ions at a dose of 1E13 to 1E16 atoms/cm 2 and an energy of 0 KeV to 200 KeV, and the heavily doped p-type region is formed by implanting p-type boron or boron difluoride ions at a dose of 1E13 to 1E16 atoms/cm 2 and an energy of 0 KeV to 100 KeV.
8. The method according to claim 1 , comprising the following steps in the sequence set forth:
1) growing a p-type epitaxial layer over a p-type substrate;
2) forming a gate oxide layer, a polysilicon gate, a lightly doped n-type drain region and a lightly doped n-type source region, the gate oxide layer covering a portion of the p-type epitaxial layer, the polysilicon gate covering the gate oxide layer, the lightly doped n-type source region being formed in the p-type epitaxial layer and on a first side of the polysilicon gate, the lightly doped n-type drain region being formed in the p-type epitaxial layer and on a second side of the gate oxide layer;
3) forming a moderately doped n-type region in a first portion of the lightly doped n-type drain region, the moderately doped n-type region having a depth greater than a depth of the lightly doped n-type drain region;
4) forming a p-type well in the p-type epitaxial layer and under the lightly doped n-type source region;
5) forming a heavily doped p-type region, a heavily doped n-type source region and a heavily doped n-type drain region, the heavily doped p-type region being formed in a first portion of the lightly doped n-type source region, the heavily doped n-type source region being formed in a second portion of the lightly doped n-type source region, the heavily doped n-type drain region being formed in a second portion of the lightly doped n-type drain region;
and
6) forming an oxide layer, at least one Faraday shield and a contact column.
9. The method according to claim 8 , wherein the moderately doped n-type region has a length of 0 μm to 4 μm, wherein a distance between the moderately doped n-type region and the polysilicon gate is greater than or equal to 0.1 μm, and wherein the depth of the moderately doped n-type region is 0.1 μm to 0.5 μm greater than the depth of the lightly doped n-type drain region.
10. The method according to claim 8 , wherein in the step 3), the lightly doped n-type drain region is formed by implanting n-type phosphorus or arsenic ions at a dose of 5E11 to 4E12 atoms/cm 2 and an energy of 100 KeV to 300 KeV.
11. The method according to claim 8 , wherein in the step 4), the p-type well is formed in the p-type epitaxial layer by implanting p-type dopant ions followed by high temperature drive-in.
12. The method according to claim 11 , wherein the p-type dopant ions are boron ions and are implanted at a dose of 1E12 to 1E14 atoms/cm 2 and an energy of 30 KeV to 80 KeV, and wherein the high temperature drive-in is performed at a temperature of 800° C. to 1200° C.
13. The method according to claim 8 , wherein in the step 5), both the heavily doped n-type source region and the heavily doped n-type drain region are formed by implanting n-type phosphorus or arsenic ions at a dose of 1E13 to 1E16 atoms/cm 2 and an energy of 0 KeV to 200 KeV, and the heavily doped p-type region is formed by implanting p-type boron or boron difluoride ions at a dose of 1 E 13 to 1E16 atoms/cm 2 and an energy of 0 KeV to 100 KeV.