Completing middle of line integration allowing for self-aligned contacts

1. A method for completing middle of line integration in a semiconductor device, comprising:

removing a hard mask layer and a set of spacers from a set of dummy gates;

depositing a liner layer over the set of dummy gates and over a source-drain region adjacent to the set of dummy gates subsequent to removing the hard mask layer and set of spacers;

removing the liner layer from at least a portion of a top surface of the set of dummy gates and from at least a portion of a top surface of the source-drain region;

depositing an inter-layer dielectric (ILD) over the set of dummy gates and over the source-drain region subsequent to the removing of the liner layer, and

removing the set of dummy gates.

2. The method of claim 1 , further comprising forming a replacement metal gate transistor.

3. The method of claim 2 , further comprising:

forming a NFET region over a substrate; and

forming a PFET region over the substrate.

4. The method of claim 3 , further comprising:

forming a set of phosphorus-doped Si (SiP) regions of a raised source-drain (RSD) in the NFET region; and

forming a set of silicon germanium (SiGe) regions of the RSD in the PFET region.

5. The method of claim 1 , the set of dummy gates comprising at least one of: poly silicon, SiOC or SiOCN.

6. The method of claim 1 , the liner layer comprising at least one of: a silicon nitride, SiOC or SiOCN.

7. The method of claim 1 , further comprising polishing the ILD.

8. The method of claim 1 , the liner layer being removed via polishing or etching.

9. The method of claim 1 , further comprising a semiconductor device formed according to the method of claim 1 .

10. A method for completing middle of line integration in a semiconductor device, comprising:

removing a hard mask layer and a set of spacers from a first gate stack and a second gate stack, the first gate stack having a first dummy gate, and the second gate stack having a second dummy gate;

depositing a liner layer over the first dummy gate and the second dummy gate and over a source-drain region adjacent to the first dummy gate and the second dummy gate subsequent to removing the hard mask layer and set of spacers;

removing the liner layer from at least a portion of a top surface of the first dummy gate and the second dummy gate and from at least a portion of a top surface of the source-drain region; and

depositing an inter-layer dielectric (ILD) over the first dummy gate and over the second dummy gate and over the source-drain region subsequent to the removing of the liner layer,

removing the first dummy gate and the second dummy gate, leaving a first recess and a second recess that are at least partially bounded by a remainder of the liner layer;

depositing a first gate in a first recess and a second gate in the second recess; and

depositing a set of contacts to the source-drain region, an alignment of the set of contacts having middle of line integration based on the remainder of the liner layer.

11. The method of claim 10 , further comprising forming a replacement metal gate transistor.

12. The method of claim 11 , the transistor comprising:

forming a NFET region over a substrate; and

forming a PFET region over the substrate.

13. The method of claim 12 , further comprising:

forming a set of phosphorus-doped Si (SiP) regions of a raised source-drain (RSD) in the NFET region; and

forming a set of silicon germanium (SiGe) regions of the RSD in the PFET region.

14. The method of claim 10 , the set of dummy gates comprising at least one of: poly silicon, SiOC or SiOCN.

15. The method of claim 10 , the liner layer comprising at least one of: a silicon nitride, SiOC or SiOCN.

16. The method of claim 10 , further comprising polishing the ILD.

17. The method of claim 10 , the liner layer being removed via polishing or etching.

18. The method of claim 10 , further comprising a semiconductor device formed according to the method of claim 1 .

19. A method for completing middle of line integration in a semiconductor device, comprising:

identifying a location for a self-aligned contact to a source-drain region adjacent to a first gate stack and a second gate stack of a semiconductor device, the first gate stack having a first dummy gate and the second gate stack having a second dummy gate;

removing a hard mask layer and a set of spacers from the first gate stack and the second gate stack;

depositing a liner layer over the first dummy gate and the second dummy gate and over the source-drain region subsequent to removing the hard mask layer and set of spacers;

removing the liner layer from at least a portion of a top surface of the first dummy gate and the second dummy gate and from at least a portion of a top surface of the source-drain region;

depositing an inter-layer dielectric (ILD) over the set of dummy gates and over the source-drain region subsequent to the removing of the liner layer, and

removing the first dummy gate and the second dummy gate, leaving a first recess and a second recess that are at least partially bounded by a remainder of the liner layer;

depositing a first gate in a first recess and a second gate in the second recess; and

depositing a set of contacts to the source-drain region, an alignment of the set of contacts having middle of line integration based on the remainder of the liner layer.

20. The method of claim 19 , further comprising a semiconductor device formed according to the method of claim 1 .