RF LDMOS DEVICE AND FABRICATION METHOD THEREOF
A radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) device includes a substrate, a p-type epitaxial layer, a p-type well, a lightly doped n-type drain region, a gate oxide layer, a polysilicon gate, a dielectric layer and a Faraday shield. The Faraday shield includes: a horizontal portion covering a portion of the polysilicon gate and isolated from the polysilicon gate by the dielectric layer; a step-like portion with at least two steps covering a portion of the lightly doped n-type drain region and isolated from the lightly doped n-type drain region by the dielectric layer; and a vertical portion connecting the horizontal portion with the step-like portion and isolated from the polysilicon gate and the lightly doped n-type drain region by the dielectric layer. A method of fabricating such an RF LDMOS device is also disclosed.
1 . A radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) device, comprising:
a substrate;
a p-type epitaxial layer on the substrate;
a p-type well in a first portion of the p-type epitaxial layer;
a lightly doped n-type drain region in a second portion of the p-type epitaxial layer and separated from the p-type well;
a gate oxide layer covering a portion of the p-type well and a portion of the p-type epitaxial layer between the p-type well and the lightly doped n-type drain region;
a polysilicon gate covering the gate oxide layer;
a dielectric layer covering the polysilicon gate and a portion of the lightly doped n-type drain region; and
a Faraday shield formed of a single metal layer and comprising:
a horizontal portion covering a portion of the polysilicon gate and isolated from the polysilicon gate by the dielectric layer;
a step-like portion covering a portion of the lightly doped n-type drain region and isolated from the lightly doped n-type drain region by the dielectric layer, the step-like portion having a step-like top surface with at least two step portions and a height of the at least two step portions increasing progressively in a direction from the p-type well to the lightly doped n-type drain region; and
a vertical portion connecting the horizontal portion with the step-like portion, the vertical portion being isolated from the polysilicon gate and the lightly doped n-type drain region by the dielectric layer.
2 . The RF LDMOS device according to claim 1 , wherein the step-like portion has a step-like top surface with two step portions and a height of the two step portions increases progressively in a direction from the p-type well to the lightly doped n-type drain region.
3 . The RF LDMOS device according to claim 1 , wherein the step-like portion has a step-like top surface with three step portions and a height of the three step portions increases progressively in a direction from the p-type well to the lightly doped n-type drain region.
4 . The RF LDMOS device according to claim 1 , wherein a portion of the dielectric layer between a first step portion nearest to the gate oxide layer and the lightly doped n-type drain region has a thickness of 10 nm to 800 nm, wherein a portion of the dielectric layer between a former step portion and the lightly doped n-type drain region has a thickness of 10 nm to 100 nm smaller than a thickness of a portion of the dielectric layer between a latter step portion and the lightly doped n-type drain region, and wherein each step portion of the step-like portion has a length of 0.01 μm to 3 μm.
5 . The RF LDMOS device according to claim 1 , wherein a portion of the dielectric layer between the vertical portion and the polysilicon gate has a thickness of 0.001 μm to 0.3 μm.
6 . The RF LDMOS device according to claim 1 , wherein the horizontal portion has a length of 0 μm to 1 μm.
7 . The RF LDMOS device according to claim 1 , further comprising:
a heavily doped n-type source region in an upper portion of the p-type well; and
a heavily doped n-type drain region in the lightly doped n-type drain region and proximate to an edge of the lightly doped n-type drain region that is farther from the gate oxide layer,
wherein both the heavily doped n-type source region and the heavily doped n-type drain region have an n-type dopant concentration higher than an n-type dopant concentration of the lightly doped n-type drain region.
8 . A method of fabricating a radio frequency (RF) laterally diffused metal oxide semiconductor (LDMOS) device, comprising the steps of:
providing a substrate;
forming a p-type epitaxial layer over the substrate;
forming a p-type well in a first portion of the p-type epitaxial layer;
forming a lightly doped n-type drain region in a second portion of the p-type epitaxial layer, the lightly doped n-type drain region being separated from the p-type well;
forming a gate oxide layer and a polysilicon gate, the gate oxide layer covering a portion of the p-type well and a portion of the p-type epitaxial layer between the p-type well and the lightly doped n-type drain region, the polysilicon gate covering the gate oxide layer;
depositing a dielectric layer over the polysilicon gate and a portion of the lightly doped n-type drain region; and
forming a Faraday shield, the Faraday shield including:
a horizontal portion covering a portion of the polysilicon gate and isolated from the polysilicon gate by the dielectric layer;
a step-like portion covering a portion of the lightly doped n-type drain region and isolated from the lightly doped n-type drain region by the dielectric layer, the step-like portion having a step-like top surface with at least two step portions and a height of the at least two step portions increasing progressively in a direction from the p-type well to the lightly doped n-type drain region; and
a vertical portion connecting the horizontal portion with the step-like portion, the vertical portion being isolated from the polysilicon gate and the lightly doped n-type drain region by the dielectric layer.
9 . The method according to claim 8 , wherein a portion of the dielectric layer between a first step portion nearest to the gate oxide layer and the lightly doped n-type drain region has a thickness of 10 nm to 800 nm, wherein a portion of the dielectric layer between a former step portion and the lightly doped n-type drain region has a thickness of 10 nm to 100 nm smaller than a thickness of a portion of the dielectric layer between a latter step portion and the lightly doped n-type drain region, and wherein each step portion of the step-like portion has a length of 0.01 μm to 3 μm.
10 . The method according to claim 8 , wherein a portion of the dielectric layer between the vertical portion and the polysilicon gate has a thickness of 0.001 μm to 0.3 μm.
11 . The method according to claim 8 , wherein the horizontal portion has a length of 0 μm to 1 μm.
12 . The method according to claim 8 , wherein the step-like portion has a step-like top surface with two step portions and a height of the two step portions increases progressively in a direction from the p-type well to the lightly doped n-type drain region.
13 . The method according to claim 8 , wherein the step-like portion has a step-like top surface with three step portions and a height of the three step portions increases progressively in a direction from the p-type well to the lightly doped n-type drain region.
14 . The method according to claim 8 , further comprising the steps of:
forming a heavily doped n-type source region in an upper portion of the p-type well; and
forming a heavily doped n-type drain region in the lightly doped n-type drain region and proximate to an edge of the lightly doped n-type drain region that is farther from the gate oxide layer,
wherein both the heavily doped n-type source region and the heavily doped n-type drain region have an n-type dopant concentration higher than an n-type dopant concentration of the lightly doped n-type drain region.