Imagers with improved analog-to-digital circuitry
View Patent ↗An imager may include an array of pixels. The pixel array may be arranged in rows and columns. Each pixel of the pixel array may include a photodiode that is coupled to a floating diffusion region by a transfer gate. A source-follower transistor may be coupled between the floating diffusion region and a pixel output node. The imager may include ramp circuitry that provides a ramp signal to the floating diffusion region. A capacitor interposed between the ramp circuitry and the floating diffusion region may be used in conveying the ramp signal to the floating diffusion region. The pixel may be coupled to a comparator that is implemented using separate circuitry or may include portions of the pixel.
1. A pixel array, comprising:
an imaging pixel having a floating diffusion region; and
ramp circuitry that provides a ramp signal to the floating diffusion region of the imaging pixel, wherein the imaging pixel comprises
a photodiode;
a transfer gate that is coupled between the photodiode and the floating diffusion region;
a source-follower transistor having a gate terminal coupled to the floating diffusion region;
supply circuitry;
a row select transistor coupled between the ramp circuitry and the floating diffusion region; and
a reset transistor coupled between the floating diffusion region and the supply circuitry wherein the reset transistor has a gate terminal that receives a reset signal, wherein the supply circuitry provides a control signal to a source-drain terminal of the reset transistor, and wherein the reset transistor uses the reset signal and the control signal to selectively enable and disable the source-follower transistor.
2. The pixel array defined in claim 1 further comprising a capacitor that is coupled between the floating diffusion region and a signal path that is coupled to the ramp circuitry, wherein the ramp signal is conveyed over the capacitor and the signal path to the floating diffusion region of the imaging pixel.
3. The pixel array defined in claim 2 wherein the image pixel comprises a given image pixel of a plurality of image pixels arranged in rows and columns.
4. The pixel array defined in claim 3 wherein the signal path extends across a given row of the plurality of image pixels.
5. The pixel array defined in claim 3 wherein the signal path extends across a given column of the plurality of image pixels.
6. The pixel array defined in claim 2 wherein the imaging pixel further comprises:
a differential pair of transistors that forms a comparator, wherein a given transistor of the differential pair is coupled to the floating diffusion region and serves as a source-follower amplifier for the image pixel.
7. The pixel array defined in claim 1 further comprising a comparator that receives a pixel output signal of the imaging pixel.
8. The pixel array defined in claim 7 wherein the comparator comprises:
a comparator output that provides a comparator output signal;
a first input that receives the pixel output signal; and
a second input that is coupled to the comparator output by a feedback path.
9. The pixel array defined in claim 8 wherein the feedback path comprises a switch that is interposed between the second input and the comparator output.
10. The pixel array defined in claim 9 further comprising a capacitor coupled between the second input and a ground terminal.
11. The pixel array defined in claim 10 further comprising:
analog-to-digital circuitry that is coupled to the comparator output.
12. An image pixel, comprising:
a photodiode;
a transfer gate that is coupled between the photodiode and a floating diffusion region;
a source-follower transistor coupled to the floating diffusion region;
a capacitor coupled between the floating diffusion region and a ramp signal path; and
a row select transistor having a first source-drain terminal coupled to the ramp signal path and a second source-drain terminal coupled to the capacitor, wherein the row select transistor is coupled between the ramp signal path and the floating diffusion region.
13. The image pixel defined in claim 12 further comprising:
an additional row select transistor that is coupled between a source-drain terminal of the source-follower transistor and an image pixel output.
14. The image pixel defined in claim 13 , wherein a gate terminal of the row select transistor and a gate terminal of the additional row select transistor are both coupled to a single control line.
15. A system, comprising:
a central processing unit;
memory;
input-output circuitry; and
an imaging device, wherein the imaging device comprises:
a pixel array;
ramp circuitry that produces at least one ramp signal; and
a lens that focuses an image on the pixel array, wherein each pixel of the pixel array comprises:
a photodiode;
a storage node that stores charge collected by the photodiode and receives the ramp signal;
a source-follower transistor coupled between the storage node and a pixel output;
a capacitor coupled between the storage node and the ramp circuitry; and
a row select transistor having a first source-drain terminal coupled to the ramp circuitry and a second source-drain terminal coupled to the capacitor, wherein the row select transistor is coupled between the ramp circuitry and the storage node.
16. The system defined in claim 15 wherein the pixel array is arranged in rows and columns and wherein the ramp circuitry provides a respective ramp signal for each row of the pixel array.