LDMOS device with step-like drift region and fabrication method thereof
An LDMOS device is disclosed. The LDMOS device includes: a substrate having a first type of conductivity; a drift region having a second type of conductivity and a doped region having the first type of conductivity both formed in the substrate; a drain region having the second type of conductivity and being formed in the drift region, the drain region being located at an end of the drift region farther from the doped region; and a buried layer having the first type of conductivity and being formed in the drift region, the buried layer being in close proximity to the drain region and having a step-like bottom surface, and wherein a depth of the buried layer decreases progressively in a direction from the drain region to the doped region. A method of fabricating LDMOS device is also disclosed.
1. A laterally diffused metal oxide semiconductor (LDMOS) device comprising:
a substrate having a first type of conductivity;
a drift region having a second type of conductivity and being formed in the substrate;
a doped region having the first type of conductivity and being formed in the substrate, the doped region being laterally adjacent to the drift region;
a drain region having the second type of conductivity and being formed in the drift region, the drain region being located at an end of the drift region farthest from the doped region; and
a buried layer having the first type of conductivity and being formed in the drift region, the buried layer continuously extending along a straight line in a direction from the drain region to the doped region and having an end in close proximity to the drain region, the buried layer having a continuous and substantially flat upper surface along the straight line and a step-like bottom surface, and wherein a maximum depth of the buried layer decreases progressively along the straight line in the direction from the drain region to the doped region.
2. The LDMOS device according to claim 1 , wherein the first and second types of conductivity are p-type and n-type, respectively, or n-type and p-type, respectively.
3. The LDMOS device according to claim 1 , wherein a maximum depth of the buried layer is determined by a doping concentration of the drift region.
4. The LDMOS device according to claim 1 , wherein the buried layer comprises at least two laterally connected sections and wherein a maximum depth of the at least two laterally connected sections decreases progressively in the direction from the drain region to the doped region.
5. The LDMOS device according to claim 1 , further comprising:
a gate oxide layer and a polysilicon gate both on a top surface of the substrate, the gate oxide layer covering a portion of the drift region and a portion of the doped region;
sidewalls on opposite sides of the gate oxide layer and the polysilicon gate; and
a heavily doped source region having the second type of conductivity and a heavily doped channel pick-up region having the first type of conductivity both formed in the doped region, the heavily doped channel pick-up region being located at an end of the source region farthest from the drift region.