Three-dimensional semiconductor memory device and method for fabricating the same
A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.
1. A three-dimensional (3D) semiconductor memory device, comprising:
insulating layers stacked on a substrate;
horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively;
vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars and charge storage layers; and
epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures,
wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.
2. The 3D semiconductor memory device as claimed in claim 1 , wherein:
a lowermost one of the horizontal structures is in contact with the epitaxial patterns;
each of the epitaxial patterns has a recessed sidewall; and
the lowermost horizontal structure has a convex portion along the recessed sidewall of each of the epitaxial patterns.
3. The 3D semiconductor memory device as claimed in claim 1 , wherein each of the epitaxial patterns has a laterally recessed sidewall.
4. The 3D semiconductor memory device as claimed in claim 1 , wherein:
a lowermost one of the horizontal structures is thicker than others of the horizontal structures; and
top surfaces of the epitaxial patterns are higher than a top surface of the lowermost horizontal structure.
5. The 3D semiconductor memory device as claimed in claim 1 , wherein:
thicknesses of the horizontal structures are substantially equal to each other; and
the epitaxial patterns are in contact with at least two vertically adjacent horizontal structures that are closest to the substrate.
6. The 3D semiconductor memory device as claimed in claim 1 , wherein:
each of the horizontal structures further includes first and second blocking insulating layers between each of the gate electrode and the semiconductor pillars; and
the first and second blocking insulating layers each include at least one of a silicon oxide layer and an aluminum oxide layer.
7. The 3D semiconductor memory device as claimed in claim 1 , wherein:
each of the vertical structures further includes a protecting layer, and a tunnel insulating layer; and
horizontal structures adjacent to the vertical structures are in contact with the charge storage layers of the vertical structures.
8. A three-dimensional (3D) semiconductor memory device, comprising:
a lower structure including a lower gate pattern and a lower semiconductor pattern penetrating the lower gate pattern, the lower semiconductor pattern being connected to a substrate; and
an upper structure including upper gate patterns stacked on the lower structure, an upper semiconductor pattern penetrating the upper gate patterns, and a vertical insulator between the upper semiconductor pattern and the upper gate patterns, the upper semiconductor pattern being connected to the lower semiconductor pattern,
wherein:
the lower semiconductor pattern has a recessed region adjacent to the lower gate pattern; and
the recessed region of the lower semiconductor pattern is defined by incline-surfaces inclined with respect to a top surface of the substrate.
9. The 3D semiconductor memory device as claimed in claim 8 , wherein a minimum width of the lower semiconductor pattern is less than a lower width of the upper semiconductor pattern.
10. The 3D semiconductor memory device as claimed in claim 8 , wherein a maximum width of the lower semiconductor pattern is greater than a maximum width of the upper semiconductor pattern.
11. The 3D semiconductor memory device as claimed in claim 8 , wherein a vertical thickness of the lower gate pattern is less than a maximum width of the lower semiconductor pattern.
12. The 3D semiconductor memory device as claimed in claim 8 , wherein:
the lower structure includes a plurality of lower gate patterns stacked on the substrate and an insulating layer between the lower gate patterns;
a horizontal section of the lower semiconductor pattern adjacent to the insulating layer has a substantially circular shape; and
a horizontal section of the lower semiconductor pattern at the recessed region has a substantially quadrilateral shape.
13. The 3D semiconductor memory device as claimed in claim 8 , wherein a minimum width of the lower semiconductor pattern is about equal to a difference between a maximum width of the lower semiconductor pattern and a vertical thickness of the lower gate pattern.
14. The 3D semiconductor memory device as claimed in claim 8 , wherein:
the lower semiconductor pattern is formed of silicon; and
the incline-surfaces are {111} crystal planes of the silicon.
15. The 3D semiconductor memory device as claimed in claim 8 , wherein a horizontal width of the lower gate pattern is greater than a horizontal width of each of the upper gate patterns.
16. The 3D semiconductor memory device as claimed in claim 8 , further comprising a horizontal insulator between the lower gate pattern and the lower semiconductor pattern and between the vertical insulator and each of the upper gate patterns,
wherein:
the horizontal insulator between the lower gate pattern and the lower semiconductor pattern extends onto a top surface and a bottom surface of the lower gate pattern; and
the horizontal insulator between the vertical insulator and each of the upper gate patterns extends onto a top surface and a bottom surface of each of the upper gate patterns.
17. A three-dimensional (3D) semiconductor memory device, comprising:
a stack structure including:
insulating layers vertically stacked on a substrate, and
a lower gate pattern between the insulating layers; and
a lower semiconductor pattern penetrating the lower gate pattern and being connected to the substrate, the lower semiconductor pattern having a recessed region defined by incline-surfaces inclined with respect to a top surface of the substrate, and the recessed region being adjacent to the lower gate pattern,
wherein a maximum width of the recessed region in a direction vertical to the top surface of the substrate is less than a vertical distance between adjacent insulating layers.
18. The 3D semiconductor memory device as claimed in claim 17 , wherein the vertical distance between the adjacent insulating layers is less than a maximum width of the lower semiconductor pattern.
19. The 3D semiconductor memory device as claimed in claim 17 , wherein:
a horizontal section of the lower semiconductor pattern adjacent to each of the insulating layers has a substantially circular shape; and
a horizontal section of the lower semiconductor pattern at the recessed region has a substantially quadrilateral shape.
20. The 3D semiconductor memory device as claimed in claim 17 , wherein:
the lower semiconductor pattern is formed of silicon; and
the incline-surfaces are {111} crystal planes of the silicon.
21. The 3D semiconductor memory device as claimed in claim 17 , further comprising a horizontal insulator between the lower gate pattern and the lower semiconductor pattern, the horizontal insulator extending onto a top surface and a bottom surface of the lower gate pattern.
22. The 3D semiconductor memory device as claimed in claim 17 , further comprising:
upper gate patterns stacked on the lower gate pattern;
an upper semiconductor pattern penetrating the upper gate patterns and being connected to the lower semiconductor pattern; and
a vertical insulator between the upper semiconductor pattern and the upper gate patterns.
23. The 3D semiconductor memory device as claimed in claim 22 , wherein a minimum width of the lower semiconductor pattern is less than a lower width of the upper semiconductor pattern.
24. The 3D semiconductor memory device as claimed in claim 22 , wherein a maximum width of the lower semiconductor pattern is greater than a maximum width of the upper semiconductor pattern.
25. The 3D semiconductor memory device as claimed in claim 22 , wherein a horizontal width of the lower gate pattern is greater than a horizontal width of each of the upper gate patterns.