CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
1. A pair of semiconductor devices, comprising:
a first nanowire disposed over a substrate, wherein a longitudinal length of the first nanowire further comprises:
a first channel region of a group IV semiconductor material;
a first source region and a first drain region electrically coupled with the first channel region;
a first gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the first channel region; and
a second nanowire disposed over the substrate, the second nanowire further comprising:
a second channel region of a group III-V semiconductor material;
a second source region and second drain region electrically coupled with the second channel region; and
a second gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around and in continuous contact with the group III-V semiconductor materials of the second channel region.
2. The pair of semiconductor devices of claim 1 , wherein the first source region and first drain region are p-type, and wherein the second source region and second drain region are n-type to render the pair of semiconductor devices complementary.
3. The pair of semiconductor devices of claim 1 , wherein the group IV semiconductor material consists essentially of germanium (Ge).
4. The pair of semiconductor devices of claim 1 , wherein the longitudinal axis of the first channel region is disposed a first distance above the substrate and wherein the longitudinal axis of the second channel region is disposed a second distance above the substrate that is different from first distance.
5. The pair of semiconductor devices of claim 1 , wherein the second distance is at least equal to the first distance added to a thickness of the first channel region along a direction orthogonal to the substrate.
6. The pair of semiconductor devices of claim 1 , wherein the first nanowire is disposed within a first vertical stack of nanowires, wherein each nanowire in the first vertical stack has a channel region consisting essentially of the group IV material, and wherein two adjacent nanowires in the first vertical stack are physically joined at a location along the longitudinal length by an intervening crystalline semiconductor material different than the group IV material.
7. The pair of semiconductor devices of claim 6 , wherein the intervening crystalline semiconductor material is disposed within a spacer region adjacent to the first gate stack.
8. The pair of semiconductor devices of claim 6 , wherein the intervening crystalline semiconductor material is the group III-V semiconductor material.
9. The pair of semiconductor devices of claim 8 , wherein the second nanowire is disposed within a second vertical stack of nanowires, wherein each nanowire in the second vertical stack has a channel region consisting essentially of the group III-V semiconductor material, and wherein two adjacent nanowires in the second vertical stack are physically joined at a location along the longitudinal length by a second intervening crystalline semiconductor material different than the group III-V semiconductor.
10. The pair of semiconductor devices of claim 9 , wherein the intervening crystalline semiconductor material is the group III-V semiconductor material and wherein the second intervening crystalline semiconductor material is the group IV semiconductor material.
11. The pair of semiconductor devices of claim 10 , wherein the two adjacent nanowires in the first vertical stack and the two adjacent nanowires in the second vertical stack are physically joined at a location along the longitudinal length by a third intervening crystalline semiconductor material that is different than either the group IV or group III-V semiconductor material.
12. The pair of semiconductor devices of claim 11 , wherein the third intervening crystalline semiconductor material is a group IV semiconductor material.
13. The pair of semiconductor devices of claim 12 , wherein the third intervening crystalline semiconductor material is SiGe.
14. A pair of complementary transistors, comprising:
a p-type transistor disposed over a substrate, wherein a longitudinal length of the p-type transistor further comprises:
a first channel region of a group IV semiconductor material;
a p-type source and drain region electrically coupled with the first channel region;
a first gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the first channel region; and
an n-type transistor disposed over the substrate, wherein a longitudinal length of the n-type transistor further comprises:
a second channel region of a group III-V semiconductor material;
an n-type source and drain region electrically coupled with the first channel region; and
a second gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around and in continuous contact with the group III-V semiconductor material of the second channel region.
15. The pair of complementary transistors wherein the group IV semiconductor material consists essentially of germanium (Ge) and wherein the group III-V semiconductor material consists essentially of one of: GaAs, InAs, InP, and a group III-N.
16. A pair of semiconductor devices, comprising:
a first nanowire disposed over a substrate, wherein a longitudinal length of the first nanowire further comprises:
a first channel region of a group IV semiconductor material;
a first source region and a first drain region electrically coupled with the first channel region;
a first gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the first channel region; and
a second nanowire disposed over the substrate, the second nanowire further comprising:
a second channel region of a group III-V semiconductor material;
a second source region and second drain region electrically coupled with the second channel region; and
a second gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the second channel region,
wherein the first nanowire is disposed within a first vertical stack of nanowires, wherein each nanowire in the first vertical stack has a channel region consisting essentially of the group IV material, and wherein two adjacent nanowires in the first vertical stack are physically joined at a location along the longitudinal length by an intervening crystalline semiconductor material different than the group IV material wherein the intervening crystalline semiconductor material is disposed within a spacer region adjacent to the first gate stack.
17. The pair of semiconductor devices of claim 16 , wherein the first source region and first drain region are p-type, and wherein the second source region and second drain region are n-type to render the pair of semiconductor devices complementary.
18. The pair of semiconductor devices of claim 16 , wherein the group IV semiconductor material consists essentially of germanium (Ge).
19. The pair of semiconductor devices of claim 16 , wherein the longitudinal axis of the first channel region is disposed a first distance above the substrate and wherein the longitudinal axis of the second channel region is disposed a second distance above the substrate that is different from first distance.
20. The pair of semiconductor devices of claim 19 , wherein the second distance is at least equal to the first distance added to a thickness of the first channel region along a direction orthogonal to the substrate.
21. A pair of semiconductor devices, comprising:
a first nanowire disposed over a substrate, wherein a longitudinal length of the first nanowire further comprises:
a first channel region of a group IV semiconductor material;
a first source region and a first drain region electrically coupled with the first channel region;
a first gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the first channel region; and
a second nanowire disposed over the substrate, the second nanowire further comprising:
a second channel region of a group III-V semiconductor material;
a second source region and second drain region electrically coupled with the second channel region; and
a second gate stack comprising a gate insulator and a gate conductor coaxially wrapping completely around the second channel region,
wherein the first nanowire is disposed within a first vertical stack of nanowires, wherein each nanowire in the first vertical stack has a channel region consisting essentially of the group IV material, and wherein two adjacent nanowires in the first vertical stack are physically joined at a location along the longitudinal length by an intervening group III-V crystalline semiconductor material different than the group IV material,
wherein the second nanowire is disposed within a second vertical stack of nanowires, wherein each nanowire in the second vertical stack has a channel region consisting essentially of the group III-V semiconductor material, and wherein two adjacent nanowires in the second vertical stack are physically joined at a location along the longitudinal length by a second intervening crystalline semiconductor material different than the group III-V semiconductor,
wherein the intervening crystalline semiconductor material is the group III-V semiconductor material and wherein the second intervening crystalline semiconductor material,
wherein the two adjacent nanowires in the first vertical stack and the two adjacent nanowires in the second vertical stack are physically joined at a location along the longitudinal length by a third intervening crystalline semiconductor material that is different than either the group IV or group III-V semiconductor material.
22. The pair of semiconductor devices of claim 21 , wherein the group IV semiconductor material consists essentially of germanium (Ge).
23. The pair of semiconductor devices of claim 21 , wherein the longitudinal axis of the first channel region is disposed a first distance above the substrate and wherein the longitudinal axis of the second channel region is disposed a second distance above the substrate that is different from first distance.
24. The pair of semiconductor devices of claim 23 , wherein the second distance is at least equal to the first distance added to a thickness of the first channel region along a direction orthogonal to the substrate.
25. The pair of semiconductor devices of claim 21 , wherein the third intervening crystalline semiconductor material is a group IV semiconductor material.
26. The pair of semiconductor devices of claim 25 , wherein the third intervening crystalline semiconductor material is SiGe.