IP Library Granted Patent US 9,468,108
Granted Patent B2
US 9,468,108 · App. 13/987,440 · Granted Oct 11, 2016

Method and structure for forming contact pads on a printed circuit board using zero under cut technology

Inventors: Dan Turpuseema (Whitehouse Station, NJ); James V. Russell (New Hope, PA)
Assignee: Abacus Finance Group LLC
H05K3/425H05K1/113H05K1/115H05K3/0094H05K3/4007H05K3/243H05K3/427H05K2201/0959Y10T29/49156
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Quick Facts
Patent No.
US 9,468,108
App. No.
13/987,440
Granted
Oct 11, 2016
Kind
B2
Abstract

A method and an apparatus for forming a contact pad on a printed circuit board over a filled plate via or blind in which an additional metallic or a non metallic coating is applied to a final surface finished plate which encapsulates the side walls of the wear resistant surface plate, and also covers the side walls of the metal layer plated onto the filled via and the wrap around plated metal which was plated in the via and onto the surface of the base metal to the extents of the pad geometry. This prevents subsequent undermining through the etching process and ensuring the integrity and reliability of the vias' electrical connection when an underlying base metal such as but not limited to copper and the surface plated metal are formed when plating metal in the via and consequently onto the surface.

Claims (30)

1. A structure including contact pads or circuits formed on a printed circuit board (PCB) over a filed or unfilled plated via, comprising:

either an additional metallic or non-metallic coating that covering to a final surface of a finished plated circuit or pad that encapsulates side walls of a final surface plate, and also covers side walls of a metal layer plated onto a filled or unfilled via and on top of a wrap around plated metal plated in the via and onto the surface of a base metal to provide a slight undercut of panel plated metal and virtually no undercut of the base metal and of the pattern plated metal, preventing subsequent undermining through the etching process and for ensuring that the integrity and reliability of the vias electrical connection when an underlying base metal and the surface plated metal are formed when plating metal in the via and consequently on the surface wherein any excess of said coating around said pad has been removed or limited to prevent shorting of said pad's or circuitry to adjacent pads or circuitry after exposed wrapped plate and base metal layers have been etched.

2. The method according to claim 1 wherein said underlying base metal is copper.

3. A structure including contact pads or circuits formed on a printed circuit board (PCB) over a filed or unfilled plated via, comprising:

an additional metallic or non-metallic coating covering a surface and side walls of a metal layer plated onto a filled or unfilled via and on top of a wrap around plated metal that is plated in the via and onto the surface of a base metal to provide a slight undercut of panel plated metal and virtually no undercut of the base metal and of the pattern plated metal, preventing subsequent undermining through the etching process and for ensuring that the integrity and reliability of the vias electrical connection when an underlying base metal and the surface plated metal are formed when plating metal in the via and consequently on the surface wherein any excess of said coating around said pads or circuits has been removed or limited to prevent shorting of said pad's or circuitry to adjacent pads or circuits after exposed wrapped plate and base metal layers has been etched.

4. The structure according to claim 3 wherein said underlying base metal is copper.

5. A method for forming contact pads or circuits on a printed circuit board (PCB) over a filed or unfilled plated via, the steps comprising:

Applying one of either an additional metallic or non-metallic coating to a final surface of a finished plated circuit or pad encapsulating side walls of a final surface plate, and also covering side walls of a metal layer plated onto a filled or unfilled via and on top of a wrap around plated metal that is plated in the via and onto the surface of a base metal to provide a slight undercut of panel plated metal and virtually no undercut of the base metal and of the pattern plated metal preventing subsequent undermining through the etching process and for ensuring that the integrity and reliability of the vias electrical connection when an underlying base metal and the surface plated metal are formed when plating metal in the via and consequently on the surface and removing or limiting any excess of said coating around said pad to prevent shorting of said pad's or circuitry to adjacent pads or circuitry after etching exposed wrapped plate and base metal layers.

6. The method according to claim 5 wherein said coating is a permanent metal suitable for the circuit or pads end application such as but not limited to gold, palladium or Rhodium.

7. The method according to claim 5 wherein said coating is a metallic temporary etch resist to be removed after etch revealing the final surface finish suitable for the circuit or pads end application such as but not limited to gold, palladium or Rhodium.

8. The method according to claim 7 wherein said temporary etch resist is tin.

9. The method according to claim 7 wherein said coating is a temporary Polymer etch resist to be removed after etch revealing the final surface finish suitable for the circuit or pads end application such as but not limited to gold, palladium or Rhodium.

10. The method according to claim 9 wherein said polymer is a photosensitive polymer selectively removed through photolithography.

11. A method according to claim 9 wherein said polymer is a photosensitive polymer selectively removed through photolithography.

12. The method according to claim 5 wherein said coating is gold.

13. The method according to claim 5 wherein said coating is palladium.

14. The method according to claim 5 wherein said coating is Rhodium.

15. The method according to claim 5 wherein said polymer is applied with spin coating, spray coating, electrostatic spray coating, dip coating, or techniques otherwise known in the art.

16. The method according to claim 15 wherein said polymer is selectively removed through laser ablation or mechanical milling techniques.

17. The method according to claim 5 wherein preventing subsequent undermining through the etching process and for ensuring that the integrity and reliability of the vias electrical connection when an underlying base metal and the surface plated metal are formed when plating metal in the via and consequently on the surface.

18. The structure according to claim 17 wherein said underlying base metal is copper.

19. The method according to claim 5 wherein said underlying base metal is copper.

20. A method for forming contact pads or circuits on a printed circuit board (PCB) over a filed or unfilled plated via, the steps comprising:

Applying one of either an additional metallic or non-metallic coating to a surface and side walls of a metal layer plated onto a filled or unfilled via and on top of a wrap around plated metal that is plated in the via and onto the surface of a base metal to provide a slight undercut of panel plated metal and virtually no undercut of the base metal and of the pattern plated metal, preventing subsequent undermining through the etching process and for ensuring that the integrity and reliability of the vias electrical connection when an underlying base metal and the surface plated metal are formed when plating metal in the via and consequently on the surface, removing or limiting any excess of said coating around said pads or circuits to prevent shorting of said pad's or circuitry to adjacent pads or circuits after etching exposed wrapped plate and base metal layers.

21. A method according to claim 20 wherein said coating is a permanent metal suitable for the circuit or pads end application such as but not limited to gold, palladium or Rhodium.

22. A method according to claim 20 wherein said coating is a metallic temporary etch resist such as but not limited to tin to be removed after etch revealing pads and or circuits ready to accept a suitable final surface finish.

23. A method according to claim 20 wherein said coating is a temporary Polymer etch resist to be removed after etch revealing pads and or circuits ready to accept a suitable final surface finish.

24. A method according to claim 20 wherein said polymer is applied with spin coating, spray coating, electrostatic spray coating, dip coating, or techniques otherwise known in the art.

25. A method according to claim 20 wherein said polymer is selectively removed through laser ablation or mechanical milling techniques.

26. The method according to claim 20 wherein said underlying base metal is copper.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 18, 2021
From: ABACUS FINANCE GROUP, LLC
To: R & D CIRCUITS; R&D ALTANOVA, INC.
Reel/Frame 058151/0588 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 8, 2021
From: R&D CIRCUITS, INC.; R&D CIRCUITS INC.; R&D CIRCUITS,INC.
To: R&D CIRCUITS
Reel/Frame 056464/0411 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 035302 FRAME: 0394. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Apr 14, 2015
From: R & D CIRCUITS; R&D ALTANOVA, INC.
To: ABACUS FINANCE GROUP, LLC
Reel/Frame 035552/0670 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2015
From: R & D CIRCUITS; R&D ALTANOVA, INC.
To: ABACUS FINANCE GROUP, LLC
Reel/Frame 035302/0394 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2013
From: TRPUSEEMA, DAN; RUSSELL, JAMES V.
To: R&D CIRCUITS, INC.
Reel/Frame 031098/0818 →
Continuity (2)
Provisional Application 61743596 · Sep 7, 2012
Related Publication 20140069704A1 · Mar 13, 2014