IP Library Granted Patent US 9,484,803
Granted Patent B2
US 9,484,803 · App. 13/990,884 · Granted Nov 1, 2016

Method for regulating an output voltage

Inventor: Joel Turchi (Garonne sur Garonne, FR)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H02M1/42H02M1/4225H02M2001/0032Y02B70/126Y02B70/16
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Quick Facts
Patent No.
US 9,484,803
App. No.
13/990,884
Granted
Nov 1, 2016
Kind
B2
Abstract

A method for regulating an output voltage of a converter is provided in which a switching frequency of a switching device is limited in response to a signal that is representative of a magnitude of a current from an input of the converter and to a sense signal generated in response to an input voltage signal.

Claims (35)

1. A method for regulating an output voltage, comprising:

generating an input current that flows through a first inductor in response to a load condition on a converter and a switching activity of a switching device;

generating a current indicator signal that is a representation of a level of the input current;

limiting a switching frequency of the switching device in response to the current indicator signal and to a sense signal generated in response to an input voltage signal;

operating the converter in a critical conduction mode in response to the current indicator signal being greater than a first reference voltage, wherein in the critical conduction mode the input current increases from a first level to a second level over a first period of time, decreases from the second level to the first level over a second period of time, increases from the first level to the second level over a third period of time, and decreases from the second level to the first level over a fourth period of time;

operating the converter in a frequency fold-back mode in response to the current indicator signal being less than the first reference voltage, wherein in the frequency fold-back mode the input current increases from a third level to a fourth level over a fifth period of time in response to the controller generating a drive signal and the switching device being on, the input current decreases from the fourth level to the third level over a sixth period of time in response to the controller generating the drive signal that turns off the switching device, the input current remains at the third level over a seventh period of time in response to the controller generating the drive signal that leaves the switching device off, and the input current increases from the third level to the fourth level over an eighth period of time in response to the controller generating the drive signal that turns on the switching device.

2. The method of claim 1 , further including operating the converter in a critical conduction mode in response to the current indicator signal being greater than the first reference voltage.

3. The method of claim 2 , further including generating a dead-time in an inductor current in response to the current indicator signal being lower than the first reference voltage.

4. The method of claim 1 , further including reducing the switching frequency of the switching device in response to the current indicator signal being less than the preset reference voltage.

5. The method of claim 1 , further including generating a dead-time in an inductor current in response to the current indicator signal being less than the first reference voltage.

6. The method of claim 1 , further including increasing a dead-time in an inductor current in response to decreasing the current indicator signal.

7. The method of claim 1 , further including setting a duration of the dead-time in response to a difference between the first reference voltage and a sum of a level of the current indicator signal and a ramp signal.

8. The method of claim 7 , wherein the switching device comprises a power switch having a control electrode and first and second current carrying electrodes, and wherein setting the duration of the dead-time further includes synchronizing the duration to a signal at the first current carrying electrode of the power switch.

9. The method of claim 1 , further including providing a second reference voltage, the first reference voltage greater than the second reference voltage, and skipping cycles of the current from the input of the power factor correction converter in response to the current indicator signal being less than the second reference voltage.

10. The method of claim 1 , further including providing a power factor controller wherein providing the power factor controller comprises:

providing a regulator stage having first and second inputs and an output;

providing a control stage having first and second inputs and an output, the first output configured to convert a first signal into a content signal that carries information about the first signal; and

providing an output stage having first and second inputs and an output, the first input coupled to the output of the regulator stage and the second input coupled to the output of the control stage.

11. The method of claim 10 , wherein providing the control stage comprises:

providing an input stage having first and second inputs and first and second outputs;

providing a dead-time detection circuit having an input and an output, the input of the dead-time detection circuit coupled to the first output of the input stage;

providing a summer stage having first and second inputs and an output, the first input coupled to the output of the dead-time detection circuit; and

providing a clock generation circuit having an input and an output, the input coupled to the output of the summer stage.

12. The method of claim 10 , wherein providing the summer stage comprises:

providing a summer circuit having first and second inputs and an output, the output serving as the output of the summer stage;

providing a capacitor having a terminal coupled to the first input of the summer circuit;

providing a charging device coupled to the terminal of the capacitor and to the first input of the summer circuit; and

providing a switch having a first terminal and a control terminal, the control terminal coupled to the output of the dead-time detection circuit and the first terminal coupled to the terminal of the capacitor, the charging device, and the first input of the summer circuit.

13. The method of claim 10 , wherein the providing the output stage comprises:

providing a latch having first and second inputs and an output, the first input of the latch coupled to the output of the clock generation circuit; and

providing a comparator having first and second inputs and an output, the output coupled to the second input of the latch, the first input coupled to a ramp generation circuit, and the second input coupled to the output of the regulator stage.

14. The method of claim 10 , wherein providing the power factor controller further comprises:

providing a first voltage to current converter having an input and an output;

providing a second voltage to current converter having an input and an output;

providing a multiplier circuit having first and second inputs, a control input, and an output, the first input coupled to the output of the first voltage to current converter, the second input coupled to the output of the second voltage to current converter, and the output coupled to the first input of the control stage and to the second input of the summer circuit.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2013
From: TURCHI, JOEL
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 030522/0583 →
Continuity (1)
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