IP Library Patent Application 14012784
Patent Application
App. No. 14/012,784

HIGH DYNAMIC RANGE IMAGING SYSTEMS HAVING CLEAR FILTER PIXEL ARRAYS

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
14/012,784
Abstract

Imaging systems may include an image sensor and processing circuitry. An image sensor may include a pixel array having rows and columns. The array may include short and long-exposure groups of pixels arranged in a zig-zag pattern. The short-exposure group may generate short-exposure pixel values in response to receiving control signals from control circuitry over a first line and the long-exposure group may generate long-exposure pixel values in response to receiving control signals from the control circuitry over a second line. The processing circuitry may generate zig-zag-based interleaved high-dynamic-range images using the long and short-exposure pixel values. If desired, the array may include short and long-exposure sets of pixels located in alternating single pixel rows. The processing circuitry may generate single-row-based interleaved high-dynamic-range images using pixel values generated by the short and long-exposure sets.

Claims (49)

1 . An imaging system having an array of image pixels arranged in pixel rows and pixel columns, the imaging system comprising:

a first group of image pixels located in first and second pixel rows of the array;

a second group of image pixels located in the first and second pixel rows of the array, wherein the second group of image pixels is different from the first group of image pixels;

a first control line coupled to the first group of image pixels;

a second control line coupled to the second group of image pixels; and

pixel control circuitry, wherein each image pixel in the first group is configured to generate short-exposure pixel values in response to first control signals received from the pixel control circuitry over the first control line and wherein each image pixel in the second group is configured to generate long-exposure pixel values in response to second control signals received from the pixel control circuitry over the second control line.

2 . The imaging system defined in claim 1 , further comprising:

a conductive column line coupled to each pixel column; and

column readout circuitry coupled to the pixel columns through the conductive column lines, wherein the column readout circuitry is configured to read out the short-exposure pixel values from the first group of image pixels and configured to read out the long-exposure pixel values from the second group of image pixels.

3 . The imaging system defined in claim 1 , wherein the first group of image pixels comprises a first set of image pixels located in the first pixel row and a second set of image pixels located in the second pixel row, wherein the second group of image pixels comprises a third set of image pixels located in the first pixel row and a fourth set of image pixels located in the second pixel row, wherein the first set of image pixels is interleaved with the third set of image pixels, and wherein the second set of image pixels is interleaved with the fourth set of image pixels.

4 . The imaging system defined in claim 3 , wherein the first and fourth sets of image pixels are located in a first set of pixel columns of the array.

5 . The imaging system defined in claim 4 , wherein the second and third sets of image pixels are located in a second set of pixel columns of the array that is different from the first set of pixel columns.

6 . The imaging system defined in claim 5 , further comprising:

a first conductive column line coupled to the first and fourth sets of image pixels;

a second conductive column line coupled to the second and third sets of image pixels; and

column readout circuitry, wherein the column readout circuitry is coupled to the first and fourth sets of image pixels through the first conductive column line and wherein the column readout circuitry is coupled to the second and third sets of image pixels through the second conductive column line.

7 . The imaging system defined in claim 6 , wherein the first and second groups of image pixels in the array are arranged in a zig-zag pattern.

8 . The imaging system defined in claim 3 , further comprising:

an image processing engine configured to generate an interpolated short-exposure image based on the short-exposure pixel values and an interpolated long-exposure image based on the long-exposure pixel values.

9 . The imaging system defined in claim 8 , wherein the image processing engine is further configured to generate a high-dynamic-range image based on the interpolated short-exposure image and the interpolated long-exposure image.

10 . The imaging system defined in claim 3 , wherein the first, second, third, and fourth sets of image pixels each include clear image pixels having clear color filter elements.

11 . The imaging system defined in claim 10 , wherein the first and third sets of image pixels further comprise red image pixels having red color filter elements and wherein the second and fourth sets of image pixels further comprise blue image pixels having blue color filter elements.

12 . The imaging system defined in claim 1 , wherein each image pixel in the first group is configured to generate the short-exposure pixel values during a first integration time period in response to receiving the first control signals from the pixel control circuitry over the first control line and wherein each image pixel in the second group is configured to generate the long-exposure pixel values during a second integration time period that is longer than the first time period in response to receiving the second control signals from the pixel control circuitry over the second control line.

13 . An image sensor having an array of image pixels arranged in pixel rows and pixel columns, wherein the array of image pixels comprises first, second, and third consecutive pixel rows, the image sensor comprising:

a first set of image pixels located in the first pixel row;

a second set of image pixels located in the second pixel row;

a third set of image pixels located in the third pixel row, wherein the first, second, and third sets of image pixels each include at least two clear image pixels; and

pixel control circuitry, wherein the pixel control circuitry is configured to instruct each image pixel in the first and third sets of image pixels to generate short-integration pixel values and wherein the pixel control circuitry is configured to instruct each image pixel in the second set of image pixels to generate long-integration pixel values.

14 . The image sensor defined in claim 13 , wherein the second pixel row is located immediately below the first pixel row in the array and wherein the third pixel row is located immediately below the second pixel row in the array.

15 . The image sensor defined in claim 14 , further comprising:

processing circuitry, wherein the processing circuitry is configured to generate an interpolated short-integration image based on the short-integration pixel values and wherein the processing circuitry is configured to generate an interpolated long-integration image based on the long-integration pixel values.

16 . The image sensor defined in claim 15 , wherein the processing circuitry is further configured to generate an interleaved high-dynamic-range image based on the interpolated short-integration image and the interpolated long-integration image.

17 . The image sensor defined in claim 16 , wherein the first and third sets of image pixels are configured to generate the short-integration pixel values in three color channels, wherein the second set of image pixels is configured to generate the long-integration pixel values in the three color channels, and wherein the three color channels includes a clear color channel.

18 . The image sensor defined in claim 17 , wherein the first set of image pixels includes a first blue image pixel, wherein the third set of image pixels includes a second blue image pixel, wherein the second set of image pixels includes a given clear image pixel, and wherein the given clear image pixel is located immediately below the first blue image pixel and immediately above the second blue image pixel in the array of image pixels.

19 . The image sensor defined in claim 17 , wherein the first set of image pixels includes a given blue image pixel, wherein the third set of image pixels includes a given red image pixel, wherein the second set of image pixels includes a given clear image pixel, and wherein the given clear image pixel is located immediately below the given blue image pixel and immediately above the given red image pixel in the array of image pixels.

20 . A system, comprising:

a central processing unit;

memory;

input-output circuitry; and

an imaging device, wherein the imaging device comprises:

an array of image sensor pixels having pixel rows and columns, wherein the array of image sensor pixels include a first group of image pixels located in first and second pixel rows and a second group of image pixels located in the first and second pixel rows, wherein the second group of image pixels is different from the first group of image pixels;

a lens that focuses an image on the array of image sensor pixels;

a first control line coupled to the first group of image pixels;

a second control line coupled to the second group of image pixels; and

pixel control circuitry, wherein the pixel control circuitry is configured to instruct each image pixel in the first group through the first control line to generate short-integration pixel values and wherein the pixel control circuitry is configured to instruct each image pixel in the second group through the second control line to generate long-integration pixel values.

21 . The system defined in claim 20 , wherein the first group of image pixels is configured to generate the short-integration pixel values in three color channels, wherein the second group of image pixels is configured to generate the long-integration pixel values in the three color channels, and wherein the three color channels includes a clear color channel.

22 . The system defined in claim 21 , further comprising:

an image processing engine, wherein the image processing engine is configured to generate an interpolated short-integration image using the short-integration pixel values and an interpolated long-integration image using the long-integration pixel values, and wherein the image processing engine is configured to generate a high-dynamic-range image based on the interpolated short-integration image and the interpolated long-integration image.

23 . The system defined in claim 22 , wherein the first group of image pixels comprises a first set of image pixels located in the first pixel row and a second set of image pixels located in the second pixel row, wherein the second group of image pixels comprises a third set of image pixels located in the first pixel row and a fourth set of image pixels located in the second pixel row, wherein the first set of image pixels is interleaved with the third set of image pixels, wherein the second set of image pixels is interleaved with the fourth set of image pixels, and wherein the first, second, third, and fourth sets of image pixels each include clear image pixels having clear color filter elements.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2014
From: APTINA IMAGING CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034673/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2013
From: LIN, PENG; MLINAR, MARKO
To: APTINA IMAGING CORPORATION
Reel/Frame 031104/0393 →