According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input to the memory cell. The resistor is in a first path between the first input of the sense amplifier and a ground node.
1. A memory device comprising:
a memory cell comprising a variable resistance;
a sense amplifier comprising a first input and a second input, the sense amplifier outputting a signal in accordance with a difference between the first and second inputs, and being selectively coupled at the second input to the memory cell;
a resistor in a first path between the first input of the sense amplifier and a ground node; and
a second path comprising the memory cell between the second input of the sense amplifier and the ground node,
wherein the resistor has a value between a first resistance of the second path including the memory cell holding first data and a second resistance of the second path including the memory cell holding second data, and
wherein the resistor comprises one of a gate resistance, a diffusion layer resistor, a metal resistor, a transistor resistor, and a combination thereof.
2. The device of claim 1 , wherein the resistor has a value greater than or equal to 10 kΩ.
3. The device of claim 1 , wherein:
the first path includes a first transistor coupled at a first end to the first input of the sense amplifier,
the memory device further comprises a second transistor between the second input of the sense amplifier and the memory cell, and
a gate of the first transistor is coupled to a gate of the second transistor.
4. The device of claim 3 , wherein:
the first transistor clamps a potential of a second end of the first transistor, and
the second transistor clamps a potential of the second transistor at a memory cell side.
5. The device of claim 1 , wherein:
the first path includes a first transistor coupled at a first end to the first input of the sense amplifier, and
the resistor is coupled between a second end of the first transistor and the ground node.
6. The device of claim 5 , wherein:
the second path includes a second transistor coupled at a first end to the second input of the sense amplifier,
the first resistance is a resistance between a second end of the second transistor and the ground node including the memory cell holding the first data, and
the second resistance is a resistance between the second end of the second transistor and the ground node including the memory cell holding the second data.
7. The device of claim 1 , wherein:
the first path includes a first transistor, and
a first end of the first transistor is coupled to the first input of the sense amplifier, and a second end of the first transistor is directly coupled to the resistor.
8. A memory device comprising:
a memory cell with a variable resistance;
a sense amplifier comprising a first input and a second input, the sense amplifier outputting a signal in accordance with a difference between the first and second inputs, and being selectively coupled at a second input to the memory cell;
a first transistor coupled at a first end to the first input of the sense amplifier and clamping a potential of a second end thereof;
a resistor between the second end of the first transistor and a ground node; and
a second transistor coupled at a first end thereof to the second input of the sense amplifier and clamping a potential of a second end thereof,
wherein the resistor has a value between a resistance of a path between the second end of the second transistor and the ground node including the memory cell holding first data and a resistance of a path between the second end of the second transistor and the ground node including the memory cell holding second data, and
wherein the resistor comprises one of a gate resistance, a diffusion layer resistor, a metal resistor, a transistor resistor, and a combination thereof.
9. The device of claim 8 , wherein the resistor has a value greater than or equal to 10 kΩ.
10. The device of claim 8 , wherein:
a gate of the first transistor is coupled to a gate of the second transistor.
11. The device of claim 8 , wherein:
the resistor is directly coupled to the second end of the first transistor.