IP Library Granted Patent US 8,785,288
Granted Patent B2
US 8,785,288 · App. 14/024,836 · Granted Jul 22, 2014

Methods of making memory cells

Inventors: Gurtej S. Sandhu (Boise, ID); Sumeet C. Pandey (Boise, ID)
Assignee: Micron Technology, Inc.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,785,288
App. No.
14/024,836
Granted
Jul 22, 2014
Kind
B2
Abstract

Some embodiments include a memory cell having a data storage region between a pair of conductive structures. The data storage region is configured to support a transitory structure which alters resistance through the memory cell. The data storage region includes two or more portions, with one of the portions supporting a higher resistance segment of the transitory structure than another of the portions. Some embodiments include a method of forming a memory cell. First oxide and second oxide regions are formed between a pair of conductive structures. The oxide regions are configured to support a transitory structure which alters resistance through the memory cell. The oxide regions are different from one another so that one of the oxide regions supports a higher resistance segment of the transitory structure than the other.

Claims (39)

1. A method of forming a memory cell, comprising:

forming a data storage region over a first conductive structure;

forming a second conductive structure over the data storage region;

wherein the data storage region is configured to support a transitory structure which alters resistance through the memory cell;

wherein the data storage region comprises two or more portions which are physically different from one another so that one of the portions supports a higher resistance segment of said transitory structure and another of the portions supports a lower resistance segment of said transitory structure; the physical difference being present prior to formation of the transitory structure;

wherein the memory cell is formed to have multiple portions of the data storage region which support multiple lower resistance segments of said transitory structure; and

wherein at least one of the lower resistance segments has a substantially different resistance than another of the lower resistance segments.

2. A method of forming a memory cell, comprising:

forming a data storage region over a first conductive structure;

forming a second conductive structure over the data storage region;

wherein the data storage region is configured to support a transitory structure which alters resistance through the memory cell;

wherein the data storage region comprises two or more portions which are physically different from one another so that one of the portions supports a higher resistance segment of said transitory structure and another of the portions supports a lower resistance segment of said transitory structure; the physical difference being present prior to formation of the transitory structure;

wherein the memory cell is formed to have multiple portions of the data storage region which support multiple higher resistance segments of said transitory structure; and

wherein at least one of the higher resistance segments has a substantially different resistance than another of the higher resistance segments.

3. A method of forming a memory cell, comprising:

depositing a first oxide region over a first conductive structure;

depositing a second oxide region over the first oxide region;

forming a second conductive structure over the second oxide region; the first and second oxide regions together being comprised by a data storage region configured to support a transitory structure which alters resistance through the memory cell;

wherein the first oxide region is different from an-e the second oxide region so that one of the oxide regions supports a higher resistance segment of said transitory structure than the other of the oxide regions; and

wherein the difference between the first and second oxide regions is a difference in crystallinity; and wherein said difference is imparted by:

depositing the first oxide region under first conditions utilizing a first temperature and a first pressure; and

depositing the second oxide region under second conditions utilizing a second temperature and a second pressure; with the second temperate being different from the first temperature and/or with the second pressure being different from the first pressure.

4. The method of claim 3 wherein the transitory structure is a filament.

5. A method of forming a memory cell, comprising:

depositing a first oxide region over a first conductive structure;

depositing a second oxide region over the first oxide region;

forming a second conductive structure over the second oxide region; the first and second oxide regions together being comprised by a data storage region configured to support a transitory structure which alters resistance through the memory cell;

wherein the first oxide region is different from the second oxide region so that one of the oxide regions supports a higher resistance segment of said transitory structure than the other of the oxide regions; and

wherein the difference between the first and second oxide regions is a difference in density; and wherein said difference is imparted by:

depositing the first oxide region under first conditions utilizing a first temperature and a first pressure; and

depositing the second oxide region under second conditions utilizing a second temperature and a second pressure; with the second temperate being different from the first temperature and/or with the second pressure being different from the first pressure.

6. A method of forming a memory cell, comprising:

depositing a first oxide region over a first conductive structure;

depositing a second oxide region over the first oxide region;

forming a second conductive structure over the second oxide region; the first and second oxide regions together being comprised by a data storage region configured to support a transitory structure which alters resistance through the memory cell;

wherein the first oxide region is different from the second oxide region so that one of the oxide regions supports a higher resistance segment of said transitory structure than the other of the oxide regions;

wherein the difference between the first and second oxide regions is a difference in dopant concentration;

wherein the dopant is incorporated into one of the first and second oxide regions by in situ incorporation of the dopant into said one of the regions during the deposition of said one of the regions; and

wherein the dopant comprises one or more elements, other than oxygen, selected from the group consisting of group 16 of the periodic table.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (2)
Division 13464934 · May 4, 2012
Related Publication 20140011322A1 · Jan 9, 2014