Imagers with stacked integrated circuit dies

1. An imager, comprising:

an imaging die that receives light, wherein the imaging die comprises a pixel array that is arranged in rows and columns;

an image processing die that is stacked with the imaging die and processes output image signals from the imaging die; and

a plurality of through-silicon vias in the imaging die that electrically couple the imaging die to the image processing die, wherein each of the plurality of through-silicon vias is coupled to a corresponding one of the columns in the pixel array.

2. The imager defined in claim 1 , wherein the through-silicon vias in the imaging die convey the output image signals to the image processing die.

3. The imager defined in claim 2 wherein the imaging die comprises processing circuitry, wherein the pixel array receives light and generates pixel signals from the received light, and wherein the processing circuitry comprises:

sample and hold circuitry; and

amplifier circuitry.

4. The imager defined in claim 3 further comprising:

an additional plurality of through-silicon vias, wherein the image processing die generates control signals that control the imaging die and wherein the additional plurality of through-silicon vias convey the control signals to the imaging die.

5. The imager defined in claim 4 wherein the imaging die comprises a front-side illuminated imaging die.

6. The imager defined in claim 4 wherein the imaging die comprises a back-side illuminated imaging die.

7. The imager defined in claim 1 further comprising:

time multiplexing circuitry coupled between each of the plurality of through-silicon vias and each corresponding column.

8. The imager defined in claim 4 wherein the processing circuitry produces the output imaging signals and conveys the output imaging signals to the image processing die over the through-silicon vias.

9. The imager defined in claim 3 wherein the imaging die is mounted to the image processing die via solder balls and wherein the image output signals are conveyed from the imaging die to the image processing die via the solder balls.

10. An integrated circuit package, comprising:

a first integrated circuit die that includes a pixel array that generates pixel signals, wherein the first integrated circuit die comprises time multiplexing circuitry;

a second integrated circuit die stacked with the first integrated circuit die, wherein the second integrated circuit die generates a first set of control signals that control the pixel array of the first integrated circuit die, and wherein the second integrated circuit die generates a second set of control signals that control the time multiplexing circuitry.

11. The integrated circuit package defined in claim 10 wherein the first integrated circuit die comprises:

a substrate layer;

a pixel layer in which the pixel array is formed; and

at least one patterned metal layer.

12. The integrated circuit defined in claim 11 wherein the substrate layer of the first integrated circuit die is mounted to the second integrated circuit die, wherein the pixel layer covers the substrate layer, and wherein the at least one patterned metal layer covers the pixel layer.

13. The integrated circuit package defined in claim 12 wherein the first integrated circuit die further comprises:

a through-silicon via that extends through the substrate layer, the pixel layer, and the at least one patterned metal layer, wherein the through-silicon via conveys at least one of the first and second sets of control signals from the second integrated circuit die to the pixel array of the first integrated circuit die.

14. The integrated circuit package defined in claim 11 wherein the pixel array receives light through the substrate layer and generates the pixel signals from the received light, wherein the first integrated circuit die provides the generated pixel signals to the second integrated circuit die.

15. A system, comprising:

a central processing unit;

memory;

input-output circuitry; and

an imaging device, wherein the imaging device comprises:

a first integrated circuit die comprising:

a pixel array that generates image signals in response to light;

time-multiplexing circuitry that is coupled to the pixel array; and

a plurality of processing circuits interposed between the pixel array and the time-multiplexing circuitry, wherein the plurality of processing circuits receive the image signals and generate processed signals based on the image signals, and wherein the plurality of processing circuits provide the processed signals to the time-multiplexing circuitry;

a second integrated circuit die on which the first integrated circuit die is mounted; and

a lens that focuses an image on the pixel array of the first integrated circuit die.

16. The system defined in claim 15 wherein the first integrated circuit die comprises:

a substrate; and

through-silicon vias that extend through the substrate.

17. The system defined in claim 16 wherein the first integrated circuit die comprises:

comparator circuitry that receives pixel signals from the pixel array and generates output signals, wherein the through-silicon vias convey the output signals from the comparator circuitry to the second integrated circuit die.

18. The system defined in claim 16 wherein the second integrated circuit die comprises:

analog-to-digital converter circuitry that receives the output signals from the first integrated circuit die and produces digital output signals;

image processor circuitry that receives and processes the digital output signals; and

control circuitry that produces control signals for the pixel array, wherein the control signals are conveyed from the second integrated circuit die to the pixel array of the first integrated circuit die over the through-silicon vias.