Methods and apparatuses for alternate clock selection
Apparatuses and methods are disclosed, such as those including an oscillator circuit that generates an alternate clock. A multiplexing circuit can be coupled to the alternate clock and an input clock. The alternate clock has a more accurate duty cycle than the input clock. A clock path can be coupled to an output of the multiplexing circuit. The more accurate alternate clock can be coupled to the clock path during a test mode.
1. An apparatus comprising:
an oscillator circuit to provide a first clock signal;
a multiplexing circuit coupled to receive the first clock signal and a second clock signal, wherein a duty cycle of the first clock signal is closer to a target duty cycle for the apparatus than a duty cycle of the second clock signal; and
a clock path coupled to an output of the multiplexing circuit, wherein the clock path comprises a plurality of entry points, each of the plurality of entry points coupled to an output of the multiplexing circuit.
2. The apparatus of claim 1 wherein the target duty cycle is a 50% duty cycle.
3. The apparatus of claim 1 wherein the clock path comprises:
a delay-locked loop coupled to the output of the multiplexing circuit; and
a trim circuit coupled to the delay-locked loop.
4. The apparatus of claim 3 wherein the trim circuit is an output high trim circuit.
5. The apparatus of claim 1 wherein the oscillator circuit comprises a phase-locked loop with a voltage controlled oscillator.
6. The apparatus of claim 5 wherein the voltage controlled oscillator is a tetrahedral oscillator.
7. The apparatus of claim 5 wherein the phase-locked loop with voltage controlled oscillator is coupled to receive the second clock signal.
8. An apparatus comprising:
a multiplexing circuit having first and second clock inputs, the multiplexing circuit to select the first clock input during a first mode of operation and to select the second clock input during a second mode of operation;
an oscillator circuit coupled to the multiplexing circuit, the oscillator circuit to provide a clock signal to the first clock input; and
a clock path having a plurality of entry points, each of the plurality of entry points coupled to an output of the multiplexing circuit.
9. The apparatus of claim 8 wherein a duty cycle of the clock signal provided to the first clock input is closer to a 50% duty cycle than a duty cycle of a clock signal provided to the second clock input.
10. The apparatus of claim 8 wherein the oscillator circuit comprises a tetrahedral oscillator.
11. The apparatus of claim 8 and further comprising a strobe output coupled to the clock path.
12. The apparatus of claim 8 and further comprising:
a memory array; and
a data latch coupled to the memory array and having a clock input coupled to the clock path.
13. A memory device comprising:
a memory array;
a data latch coupled to the memory array; and
a clock circuit coupled to the data latch, the clock circuit comprising:
a multiplexing circuit coupled to receive a first clock signal and a second clock signal, the multiplexing circuit having a selection input for selecting the first clock signal for a normal operation mode and the second clock signal for a test mode;
an oscillator circuit coupled to the multiplexing circuit, wherein the oscillator circuit provides the second clock signal in response to the first clock signal such that a duty cycle of the second clock signal is closer to a target duty cycle for the memory device than a duty cycle of the first clock signal;
a delay-locked loop coupled to the multiplexing circuit to adjust a phase of one of the first or the second clock signals; and
an output high trim circuit coupled between the delay-locked loop and the data latch, the output high trim circuit to be configured in response to the second clock signal.
14. The memory device of claim 13 wherein the oscillator circuit is configured to provide the second clock signal such that it is synchronized with the first clock signal.
15. A method comprising:
selecting a first clock signal in response to entry into a test mode of a memory device, wherein selecting the first clock signal causes the first clock signal to be provided to a clock path entry point; and
selecting a second clock signal in response to entry into a normal operation mode of the memory device, wherein selecting the second clock signal causes the second clock signal to be provided to the clock path entry point and wherein the first clock signal has a duty cycle that is closer to a target duty cycle for the memory device than the second clock signal.
16. The method of claim 15 and further comprising:
trimming a circuit of the memory device in response to the first clock signal.
17. The method of claim 15 and further comprising generating the first clock signal with an oscillator, wherein the first clock signal is synchronized to the second clock signal.
18. The method of claim 15 and further comprising generating the first clock signal with a phase-locked loop having a tetrahedral oscillator, wherein the first clock signal is synchronized to the second clock signal.