Multi-word line erratic programming detection
Techniques are presented to detect word line failures (such as word line to word line shorts, control gate to substrate shorts, broken word lines, and so on) in non-volatile memory arrays. A first simultaneous read of multiple word lines is performed, followed by a second simultaneous read of the same word lines, where the read conditions of the two reads are shifted by a margin. For example, one of the read could use a standard read voltage on the word lines, while the other read could shift these levels slightly higher. The results of the two reads can then be compared on a bit line by bit line basis, XOR-ing the results to determine is the set of word lines may include any defective members.
1. A method of determining whether a memory circuit, including an array of a plurality of memory cells formed along word lines and bit lines, has defective word lines, the method comprising:
performing a program operation to write to one of two or more data states to each of a plurality of memory cells formed along a first plurality of selected word lines and a first set of one or more selected bits lines;
subsequently performing first and second composite sensing operations, each including:
concurrently applying to each of the first plurality of selected word lines a corresponding sensing voltage to distinguish between a first pair of the data states, wherein the values of the sensing voltages for the second composite sensing operation are shifted by a margin voltage relative to the corresponding sensing voltages for the first composite sensing operation; and
concurrently performing, for each of the one or more selected bit lines, a first combined sensing operation of the corresponding plurality of memory cells along the plurality of selected word lines while said sensing voltages are applied thereto, where the result of the first combined sensing operation for each of the selected bit lines is dependent upon the state of the plurality of memory cells therealong on the first plurality of selected word lines;
performing a comparison of the results of the first composite sensing operation to the result of the second composite sensing operation on a bit line by bit line basis for each of the first set of selected bit lines; and
based upon the comparison, determining whether the first plurality of bit lines includes any defective word lines.
2. The method of claim 1 , wherein the comparison includes performing for each of the first set of selected bit lines an exclusive OR (XOR) operation of the result of the first composite sensing operation with the second composite sensing operation.
3. The method of claim 2 , wherein the determining includes determining the number of “1” values resulting from the XOR operation.
4. The method of claim 3 , wherein the determining includes determining whether the number of “1” values resulting from the XOR operation exceeds a predetermined limit.
5. The method of claim 2 , wherein the determining depends upon the location of “1” values resulting from the XOR operation.
6. The method of claim 1 , wherein the first and second composite sensing operations further comprise:
for each of the first set of selected bit lines storing the result of the first and second composite sensing operations in a respective first and second data latch associated with each of the selected bit lines.
7. The method of claim 6 , wherein the comparison includes, for each of the first set of selected bit lines XOR-ing the contents of the first and second associated data latches and storing the result in a third data latch associated with the corresponding selected bit line.
8. The method of claim 7 , wherein determining whether the first plurality of bit lines includes any defective word lines includes counting the number of “1” values the in the third associated data latches.
9. The method of claim 1 , wherein for both the first and second composite sensing operations the same sensing voltage is applied to each of the first plurality of selected word lines.
10. The method of claim 9 , wherein the memory cells are operated as binary memory cells and the sensing voltages applied in the first and second composite sensing operations distinguish between the two data states of the binary memory cells.
11. The method of claim 9 , wherein the memory cells are operated as multi-state memory cells and the sensing voltages of the first and second composite sensing operations distinguish between a first and a second of the multi-states.
12. The method of claim 11 , wherein the first and second of the multi-states correspond to the two most highly programmed of the multi-states.
13. The method of claim 11 , wherein the first and second of the multi-states correspond to the erased state and the multi-state adjacent to the erased state.
14. The method of claim 11 , further comprising:
subsequent to performing the first and second composite sensing operations, performing third and fourth composite sensing operations, each including:
concurrently applying to each of the first plurality of selected word lines a corresponding sensing voltage to distinguish between a second pair of the data states, wherein the values of the sensing voltages for the fourth composite sensing operation are shifted by a margin voltage relative to the corresponding sensing voltages for the third composite sensing operation, and wherein at least one of the second pair of the data states is not one of the first pair of data states; and
concurrently performing, for each of the one or more selected bit lines, a combined sensing operation of the corresponding plurality of memory cells along the plurality of selected word lines while said sensing voltages are applied thereto, where the result of the combined sensing operation for each of the selected bit lines is dependent upon the state of the plurality of memory cells therealong on the first plurality of selected word lines; and
performing a comparison of the results of the third composite sensing operation to the result of the fourth composite sensing operation on a bit line by bit line basis for each of the first set of selected bit lines, wherein the determining whether the first plurality of bit lines includes any defective word lines is further based upon the comparison of the results of the third composite sensing operation to the result of the fourth composite sensing operation.
15. The method of claim 1 , wherein the comparison is performed on the memory circuit.
16. The method of claim 1 , wherein the first plurality of word lines are non-adjacent.
17. The method of claim 1 , wherein the array is formed according to a NAND-type architecture and the sensed memory cells along each of the selected bit lines are from a common NAND string, and wherein the composite sensing operation further includes applying a voltage to the non-selected word-lines of the common NAND strings whereby the memory cells there along do not contribute to the result of the combined sensing operation.
18. The method of claim 1 , wherein the memory array is a flash memory array formed of a plurality of erase blocks and the first plurality of selected word lines belong to a first of the erase blocks, the method further comprising:
in response to determining that the first plurality of word lines includes a defective word line, mapping out the first erase block as defective.
19. The method of claim 1 , further comprising:
in response to determining that the first plurality of bit lines includes a defective word line, determines those of the first plurality of word lines that are defective.