Imaging systems with circuit element in carrier wafer
View Patent ↗An imaging system may include an image sensor package with an image sensor wafer mounted on a carrier wafer, which may be a silicon substrate. A capacitor may be formed in the carrier wafer. Trenches may be etched in a serpentine pattern in the silicon substrate. Conductive plates of the capacitor may be formed at least partially in the trenches. An insulator material may be formed between the capacitor and the silicon substrate. A dielectric layer may be formed between the conductive plates of the capacitor. The image sensor package may be mounted on a printed circuit board via a ball grid array. Conductive vias may electrically couple the capacitor and the image sensor wafer to the printed circuit board.
1. Apparatus, comprising:
a carrier wafer comprising a silicon substrate with a surface, wherein a trench is formed in the surface;
an image sensor wafer having an array of image pixels, wherein the image sensor wafer is mounted on the carrier wafer; and
a circuit element that is at least partially formed within the trench in the surface of the carrier wafer.
2. The apparatus defined in claim 1 , wherein the circuit element comprises a capacitor.
3. The apparatus defined in claim 2 , further comprising an insulator material interposed between the silicon substrate and the capacitor, wherein the capacitor comprises:
a bottom cell plate formed over the silicon substrate;
a top cell plate formed over the bottom cell plate; and
a dielectric layer interposed between the top cell plate and the bottom cell plate.
4. The apparatus defined in claim 3 , wherein the bottom cell plate, the top cell plate, the insulator material, and the dielectric layer are at least partially formed within the trench.
5. The apparatus defined in claim 3 , wherein the dielectric material is a high-k material.
6. The apparatus defined in claim 3 , further comprising an oxide layer formed over the top cell plate and wherein the oxide layer has a top surface that forms a top surface of the carrier wafer.
7. The apparatus defined in claim 3 , further comprising a printed circuit substrate, wherein the carrier wafer is mounted to the printed circuit substrate.
8. The apparatus defined in claim 4 , wherein the trench is formed in a serpentine pattern.
9. The apparatus defined in claim 7 , further comprising a conductive via that passes from a top side of the carrier wafer through the carrier wafer to an opposing bottom side of the carrier wafer, wherein the conductive via electrically couples circuitry on the printed circuit substrate to image sensor circuitry on the image sensor wafer.
10. The apparatus defined in claim 9 , further comprising first and second additional conductive vias that pass through at least a portion of the carrier wafer, wherein the first and the second additional conductive vias respectively couple the top and the bottom cell plates of the capacitor to circuitry on the printed circuit substrate.
11. The apparatus defined in claim 10 , wherein the carrier wafer is mounted to the printed circuit substrate using solder.
12. A method of forming an image sensor package, wherein the image sensor package comprises an image sensor wafer having an array of image pixels, comprising:
thinning the image sensor wafer;
forming a circuit element in a carrier wafer; and
bonding the carrier wafer to the image sensor wafer.
13. The method defined in claim 12 , wherein the carrier wafer comprises a silicon substrate and wherein forming the circuit element in the carrier wafer comprises forming a capacitor in the silicon substrate.
14. The method defined in claim 12 , further comprising bonding a glass layer to the image sensor wafer and mounting the image sensor package to a printed circuit substrate.
15. The method defined in claim 13 , wherein forming the capacitor comprises:
etching a trench in the silicon substrate;
depositing an insulator material in the trench;
forming a first conductive plate over the insulator material;
depositing a dielectric material over the first conductive plate; and
forming a second conductive plate over the dielectric material.
16. The method defined in claim 15 , further comprising etching portions of the first conductive plate and the second conductive plate.
17. A system, comprising:
a central processing unit;
memory;
input-output circuitry; and
an imaging device, wherein the imaging device comprises:
an image sensor wafer;
a carrier wafer bonded to the image sensor wafer, wherein the carrier wafer comprises a silicone substrate having a trench; and
at least one circuit element at least partly formed in the trench in the carrier wafer.
18. The system defined in claim 17 , wherein the at least one circuit element comprises a capacitor.
19. The system defined in claim 17 , wherein the at least one circuit element comprises an inductor.
20. The system defined in claim 17 , wherein the at least one circuit element comprises a resistor.