IP Library Granted Patent US 9,295,150
Granted Patent B2
US 9,295,150 · App. 14/035,957 · Granted Mar 22, 2016

Method for manufacturing a printed circuit board

Inventor: Wen-Hung Hu (Taoyuan, TW)
Assignee: Zhen Ding Technology Co., Ltd.
H05K1/0298H05K3/4602H05K1/115H05K3/421H05K2201/096H05K2201/09509H05K2201/09563Y10T29/49165
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Quick Facts
Patent No.
US 9,295,150
App. No.
14/035,957
Granted
Mar 22, 2016
Kind
B2
Abstract

A printed circuit board includes a first, second, and third dielectric layers, and a first, second, and third trace layers. The first trace layer and the second trace layer are formed on opposite surfaces of the first dielectric layer. The second dielectric layer is formed on the second trace layer, a first blind hole is defined in the first surface and terminated at a position in the first dielectric layer, a first conductive via is formed in the first blind hole. A second blind hole is formed in the second dielectric layer and the first dielectric layer. A second conductive via is formed in the second blind hole. The third trace layer is electrically connected with the second conductive via. The first trace layer is electrically connected with the second trace layer through the first conductive via and the second conductive via.

Claims (17)

1. A method for manufacturing a printed circuit board, comprising:

providing a core substrate comprising a first dielectric layer, the first dielectric layer having a first surface and an opposite second surface;

defining a first blind hole in the first surface of core substrate, the first blind hole extending toward the second surface and terminating at a position between the first and second surfaces of the first dielectric layer;

forming a first conductive via in the first blind hole;

forming a first trace layer on the first surface and a second trace layer on the second surface;

laminating a second dielectric layer on the second trace layer and the first dielectric layer exposed from the second trace layer;

forming a second blind hole passing through the second dielectric layer and a complementary portion of the first dielectric layer, the first conductive via exposed from the second blind hole; and

forming a second conductive via in the second blind hole, the second conductive via contacting the first conductive via and being electrically connected with the first conductive via, and forming a third trace layer on a surface of the second dielectric layer, the first trace layer electrically connected with the third trace layer through the first conductive via and the second conductive via.

2. The method of claim 1 , wherein a depth of the first blind hole in the first dielectric layer is in a range from a half to three quarters of the thickness of the dielectric layer.

3. The method of claim 1 , wherein a third dielectric layer is laminated on the first trace layer when laminating the second dielectric layer.

4. The method of claim 3 , further comprising:

forming a third blind hole and a fourth blind hole in the third dielectric layer, the third blind hole aligned with the first blind hole, the fourth blind hole aligned with a trace of the first trace layer;

forming a third conductive via in the third blind hole and a fourth conductive via in the fourth blind hole;

forming a fourth trace layer on a surface of the second dielectric layer facing away from the first dielectric layer, the third conductive via and the fourth conductive via electrically connected with the fourth trace layer, the fourth trace layer electrically connected with the first conductive via through the third conductive via, the fourth trace layer electrically connected with the first trace layer through the fourth conductive via.

5. The method of claim 4 , further comprising forming a first solder mask layer on the fourth trace layer, a first opening defined in the first solder mask, a portion of the fourth trace exposed from the first opening serving as an electrically connecting pad.

6. The method of claim 5 , further comprising forming a first protection layer on the connecting pad and forming a solder bump on the first protection layer.

7. The method of claim 4 , wherein a fifth blind hole is defined in the second dielectric layer when defining the second blind hole, a fifth conductive via is formed in the fifth blind hole when forming the second conductive via, the fifth blind hole is aligned with a trace of the second trace layer, the second conductive via is electrically connected with the second and the third trace layer.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2023
From: QI DING TECHNOLOGY QINHUANGDAO CO., LTD.; ZHEN DING TECHNOLOGY CO., LTD.
To: LEADING INTERCONNECT SEMICONDUCTOR TECHNOLOGY QINHUANGDAO CO., LTD.; ZHEN DING TECHNOLOGY CO., LTD.
Reel/Frame 064899/0050 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2016
From: ZHEN DING TECHNOLOGY CO., LTD.
To: QI DING TECHNOLOGY QINHUANGDAO CO., LTD.; ZHEN DING TECHNOLOGY CO., LTD.
Reel/Frame 039822/0459 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2013
From: HU, WEN-HUNG
To: ZHEN DING TECHNOLOGY CO., LTD.
Reel/Frame 031273/0024 →
Priority Claims (1)
CN 2012 1 0363035 · Sep 26, 2012 · national
Continuity (1)
Related Publication 20140083757A1 · Mar 27, 2014