Semiconductor device

1. A semiconductor device, comprising:

a well region formed in a substrate;

a gate electrode formed over the well region;

a first body region having a channel region formed in the well region and having an opposite conductive type to the well region and partially overlapping the gate electrode;

a second body region having a channel extension region formed in the well region and being spaced apart from the first body region and having an opposite conductive type to the well region and fully overlapping the gate electrode,

wherein the well region comprises a first region and a second region,

wherein the first region and the second region are spaced apart from each other and overlap the gate electrode,

wherein the second body region is disposed between the first region and the second region.

2. The semiconductor device of claim 1 , further comprising:

a first channel; and

a second channel,

wherein the first channel is formed by overlap of the gate electrode and the first body region; and

the second channel is formed by overlap of the gate electrode and the second body region.

3. The semiconductor device of claim 1 , wherein the channel extension region has a smaller threshold voltage than the channel region.

4. The semiconductor device of claim 1 , further comprising:

a gate insulation layer formed over the well region;

a drain region disposed in the well region; and

a source region and a pickup region disposed in the first body region.

5. The semiconductor device of claim 4 ,

wherein the second body region has a greater depth than the source region, and

the second body region has a smaller depth than the first body region from an upper surface of the substrate.

6. The semiconductor device of claim 4 , further comprising:

a isolation layer between the gate electrode and the drain region,

wherein the device isolation layer partially overlaps a portion of the gate electrode.

7. The semiconductor device of claim 4 ,

wherein the channel extension region is spaced apart from the source region.

8. The semiconductor device of claim 1 , further comprising:

a buried impurity region formed under the well region and having a higher impurity doping concentration than the well region.

9. The semiconductor device of claim 1 ,

wherein the channel region has a first threshold voltage and the channel extension region has a second threshold voltage,

wherein an off-current and on-current of the semiconductor device is controlled by the first threshold voltage and the second threshold voltage, respectively.

10. The semiconductor device of claim 1 ,

wherein the first body region has a longer width than the second body region.

11. A semiconductor device, comprising:

a well region formed in a substrate;

a gate electrode formed over the well region;

a first body region having a channel region formed in the well region and having an opposite conductive type to the well region and partially overlapping the gate electrode;

a second body region having a channel extension region formed in the well region and being spaced apart from the first body region and having an opposite conductive type to the well region and fully overlapping the gate electrode,

wherein the first body region has a higher doping concentration than the second body region.

12. A semiconductor device, comprising:

a well region formed in a substrate;

a gate electrode formed over the well region;

a first body region having a channel region formed in the well region and having an opposite conductive type to the well region and partially overlapping the gate electrode;

a second body region having a channel extension region formed in the well region and being spaced apart from the first body region and having an opposite conductive type to the well region and fully overlapping the gate electrode,

wherein the channel extension region has a longer width than the channel region.