Contact pad for semiconductor devices
Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer and/or polymer layer disposed over the substrate and a portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to an exposed portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a stepped region.
1. A semiconductor structure comprising:
a substrate having a contact pad thereon;
a passivation layer over the substrate, wherein a portion of the contact pad is exposed; and
a post passivation interconnect (PPI) over the passivation layer and the exposed portion of the contact pad, the PPI being electrically coupled to the contact pad, the PPI comprising a PPI line, a PPI pad, and a transition element interposed between the PPI line and the PPI pad, the transition element having a stepped region, the stepped region having a greater width than the PPI line.
2. The semiconductor structure of claim 1 , wherein the transition element further comprises a tapered region interposed between the stepped region and the PPI pad.
3. The semiconductor structure of claim 1 , wherein the stepped region includes a plurality of steps.
4. The semiconductor structure of claim 3 , wherein each of the plurality of steps increases in size as the steps proceed from the PPI line to the PPI pad.
5. The semiconductor structure of claim 1 , wherein the PPI pad is electrically coupled to another PPI line.
6. The semiconductor structure of claim 5 , wherein another transition element is interposed between the PPI pad and the another PPI line.
7. The semiconductor structure of claim 1 , further comprising an electrical connection coupled to the PPI pad, an edge of the electrical connection wetting terminating in the transition element.
8. The semiconductor structure of claim 1 , further comprising a polymer layer interposed between the passivation layer and the PPI.
9. The semiconductor structure of claim 1 , wherein the stepped region comprises steps on along two sides of the PPI line.
10. A semiconductor structure comprising:
a substrate having a conductive pad and one or more conductive lines formed thereon; and
conductive transition elements interposed between the conductive pad and each of the one or more conductive lines, each of the transition elements having a stepped region, the stepped region having one or more steps wherein each of the one or more steps comprises a conductive line wider than respective ones of the one or more conductive lines.
11. The semiconductor structure of claim 10 , wherein the stepped region has a single step.
12. The semiconductor structure of claim 10 , wherein the stepped region extends laterally along opposing sides of each of the conductive lines.
13. The semiconductor structure of claim 10 , wherein the transition element further comprises a tapered region interposed between the stepped region and the conductive pad.
14. The semiconductor structure of claim 10 , wherein the stepped region has a step having a width greater than about one-fifth of a diameter of the conductive pad and less than about two-fifths of the diameter of the conductive pad.
15. A method of forming a semiconductor device, the method comprising:
providing a substrate having a contact pad thereon;
forming one or more dielectric layers over the substrate, wherein a portion of the contact pad is exposed; and
forming a post-passivation interconnect (PPI) over the passivation layer and the exposed portion of the contact pad, the PPI comprising:
a PPI pad;
a PPI line extending from the contact pad toward the PPI pad; and
a stepped region interposed between the PPI line and the PPI pad, the stepped region comprising one or more steps having a greater width than the PPI line.
16. The method of claim 15 , wherein the transition element further comprises a tapered region interposed between the stepped region and the PPI pad.
17. The method of claim 15 , wherein the PPI pad is electrically coupled to another PPI line.
18. The method of claim 17 , wherein another transition element is interposed between the PPI pad and the another PPI line.
19. The method of claim 15 , further comprising an electrical connection coupled to the PPI pad, an edge of the electrical connection wetting terminating in the transition element.
20. The method of claim 15 , wherein the one or more dielectric layers comprise a passivation layer and a polymer layer.