Plug via formation with grid features in the passivation layer

1. A method of fabricating a solder bump connection, the method comprising:

forming a passivation layer on a dielectric layer;

forming a plurality of via openings extending through the passivation layer from a top surface of the passivation layer to a metal line in the dielectric layer;

forming a conductive layer on the top surface of the passivation layer and within each via opening;

planarizing the passivation layer and the conductive layer to define a first plug comprised of a plurality of sections in the via openings that are each coupled with the metal line;

forming one or more Under Bump Metallurgy (UBM) layers on the sections of the first plug; and

forming a solder bump that is coupled with the metal line by the sections of the first plug.

2. The method of claim 1 wherein each via opening has a width and a depth relative to the top surface of the passivation layer, the conductive layer on the top surface of the passivation layer has a thickness, and the width ranges from one-half of the thickness of the conductive layer to less than the depth of the via opening.

3. The method of claim 2 wherein the passivation layer has a thickness, and the width of each via opening is equal to the thickness of the passivation layer.

4. The method of claim 1 wherein forming one or more Under Bump Metallurgy (UBM) layers on the sections of the first plug comprises:

before the conductive layer is formed, forming a seed layer covering the via openings, the metal line, and the top surface of the passivation layer,

wherein the seed layer is configured to promote the formation of the conductive layer.

5. The method of claim 4 wherein forming one or more Under Bump Metallurgy (UBM) layers on the sections of the first plug further comprises:

before the seed layer is formed, forming an adhesion layer covering the via opening, the metal line, and the top surface of the passivation layer.

6. The method of claim 5 wherein planarizing the passivation layer and the conductive layer comprises:

removing the seed layer and the adhesion layer from the top surface of the passivation layer so that a top surface of the first plug is coplanar with the top surface of the passivation layer.

7. The method of claim 4 wherein forming the conductive layer comprises:

electrodepositing a conductor on the seed layer to form the conductive layer.

8. The method of claim 1 further comprising:

forming a crackstop opening extending through the passivation layer,

wherein a second plug comprised of a conductor of the conductive layer is disposed in the crackstop opening after the passivation layer and the conductive layer are planarized.

9. The method of claim 8 further comprising:

forming an adhesion layer on the top surface of the passivation layer, the first plug, and the second plug;

forming a pedestal on the adhesion layer at the location of the first plug;

after the pedestal is formed, applying a mask on the adhesion layer at a location overlying the crackstop opening; and

removing unmasked portions of the adhesion layer from the top surface of the passivation layer so that a section of the adhesion layer covers the second plug.

10. The method of claim 1 further comprising:

before the solder bump is formed, forming a pedestal on the UBM layers,

wherein the pedestal is located between the solder bump and the UBM layers.

11. The method of claim 1 wherein the via openings are arranged in a grid when formed.

12. A method comprising:

forming a passivation layer on a dielectric layer;

forming a via opening extending through the passivation layer from a top surface of the passivation layer to a metal line in the dielectric layer;

forming a plurality of fill openings extending partially through the passivation layer and located adjacent to an edge of the via opening;

forming a conductive layer on the top surface of the passivation layer and within each via opening and each fill opening; and

planarizing the passivation layer and the conductive layer to define a first plug in the via opening that is coupled with the metal line and a plurality of second plugs in the fill openings,

wherein the first plug participates in forming a solder bump connection, and the second plugs are not electrically coupled with the solder bump connection, and

wherein the passivation layer is comprised of an organic material.

13. The method of claim 12 wherein each fill opening has a width that is greater than or equal to two times a thickness of the conductive layer.

14. The method of claim 12 wherein the organic material is comprised of polyimide.

15. A method of fabricating a solder bump connection, the method comprising:

forming a passivation layer on a dielectric layer;

forming a plurality of via openings extending through the passivation layer from a top surface of the passivation layer to a metal line in the dielectric layer;

forming a conductive layer on the top surface of the passivation layer and within each via opening; and

planarizing the passivation layer and the conductive layer to define a first plug comprised of a plurality of sections in the via openings that are each coupled with the metal line,

wherein the passivation layer is comprised of an organic material.

16. The method of claim 15 wherein the organic material is comprised of photosensitive polyimide.

17. The method of claim 15 further comprising:

forming a solder bump that is coupled with the metal line by the sections of the first plug.