Forming resistive random access memories together with fuse arrays
A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.
1. An integrated circuit comprising:
a semiconductor substrate;
a chalcogenide memory array formed on said substrate, the chalcogenide memory array including a first set of parallel trenches and a second set of parallel trenches perpendicular to the first set of parallel trenches; and
a fuse array on the substrate, the fuse array including a third set of parallel trenches.
2. The integrated circuit of claim 1 wherein the third set of parallel trenches is oriented in the same direction as the first set of parallel trenches.
3. The integrated circuit of claim 1 wherein the fuse array further comprises a fourth set of parallel trenches perpendicular to the third set of parallel trenches.
4. The integrated circuit of claim 3 wherein the fourth set of parallel trenches is oriented in the same direction as the second set of parallel trenches.
5. A device comprising:
an array of chalcogenide memory cells including transistors coupled to drive each of the memory cells in the array of chalcogenide memory cells;
an array of fuse cells formed on a same substrate as the array of chalcogenide memory cells; and
continuous word lines positioned to drive a plurality of cells of the array of fuse cells simultaneously.
6. The device of claim 5 further comprising a select transistor for each fuse cell in the fuse cell array.
7. The device of claim 5 further comprising a select transistor for each of the continuous word lines.
8. The device of claim 7 wherein the select transistor is on a same side of the array as an associated fuse cell of the array of fuse cells.
9. The device of claim 5 wherein the transistors comprise bipolar junction transistors.
10. The device of claim 6 wherein the select transistor comprises an NMOS selector.