Bipolar junction transistors with self-aligned terminals
Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.
1. A method of fabricating a bipolar junction transistor, the method comprising:
forming a first layer comprised of a first semiconductor material and disposed on a substrate containing a first terminal;
forming a second layer comprised of a second semiconductor material and disposed on the first layer;
forming a patterned etch mask on the second layer;
etching a trench extending through the etch mask, the first layer, and the second layer and into the substrate so as to define a section of the first layer and a section of the second layer stacked with the section of the first layer; and
etching the substrate and the section of the second layer selectively to the section of the first layer and the etch mask so that the section of the second layer is narrowed relative to the section of the first layer to define a second terminal and a portion of the trench in the substrate is widened to undercut the section of the first layer.
2. The method of claim 1 wherein forming the trench extending through the patterned etch mask, the first layer, and the second layer and into the substrate comprises:
etching the first layer, the second layer, and the substrate with a first etching process that is selective relative to the etch mask.
3. The method of claim 2 wherein the substrate and the section of the second layer are selectively etched relative to the section of the first layer and the etch mask with a second etching process.
4. The method of claim 3 further comprising:
before the trench is formed by the first etching process, forming an etch stop layer in the substrate,
wherein the etch stop layer is configured to etch selective to a portion of the substrate between the etch stop layer and the first layer during the second etching process.
5. The method of claim 1 wherein the substrate includes a first surface that is coextensive with the trench, and further comprising:
after the substrate and the section of the second layer are etching selectively to the section of the first layer and the etch mask, forming a silicide layer on the first surface of the substrate.
6. The method of claim 5 the substrate includes a second surface that is coextensive with the trench, and further comprising:
covering the second surface of the substrate with a dielectric layer comprised of a material that prevents silicide formation.
7. The method of claim 6 further comprising:
masking the section of the first layer and the section of the second layer; and
opening a contact area on a top surface of the substrate that is separated from the first surface of the substrate by the removing the first layer and the second layer from the substrate peripheral to the second surface,
wherein the contact area is coupled by a doped region extending beneath the trench with the first terminal.
8. The method of claim 5 further comprising:
forming a contact coupled with the silicide layer on the first surface of the substrate.
9. The method of claim 1 wherein the section of the first layer includes an intrinsic base that is coextensive with the first terminal along a junction and an extrinsic base that overhangs the trench, and further comprising:
forming a dielectric layer of a local interconnect structure;
forming a contact extending through the dielectric layer to the extrinsic base; and
filling the trench with a dielectric material originating from the dielectric layer to define a trench isolation region located at least in part beneath the extrinsic base.
10. The method of claim 1 wherein the section of the second layer is coextensive with a portion of the first layer along a junction, and further comprising:
forming a dielectric layer of a local interconnect structure;
forming a contact extending through the dielectric layer to the second terminal; and
filling the trench with dielectric material from the dielectric layer to define a trench isolation region that extends beneath the first layer.
11. The method of claim 1 further comprising:
masking the section of the first layer and the section of the second layer; and
removing the first layer and the second layer from the substrate peripheral to the trench to open a contact area,
wherein the contact area is coupled by a doped region extending beneath the trench with the first terminal.