IP Library Granted Patent US 9,299,843
Granted Patent B2
US 9,299,843 · App. 14/078,701 · Granted Mar 29, 2016

Semiconductor structure and manufacturing method thereof

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Quick Facts
Patent No.
US 9,299,843
App. No.
14/078,701
Granted
Mar 29, 2016
Kind
B2
Abstract

A semiconductor structure comprises a substrate, a plurality of fins, an oxide layer and a gate structure. The fins protrude from the substrate and are separated from each other by the oxide layer. The surface of the oxide layer is uniform and even plane. The gate structure is disposed on the fins. The fin height is distance between the top of the fins and the oxide layer, and at least two of the fins have different fin heights.

Claims (20)

1. A manufacturing method of a semiconductor structure, comprising:

forming a plurality of fins on a substrate, wherein a hard mask is disposed on top of the fins, and the fins at least include a first fin and a second fin;

forming an oxide material covers the substrate, the fins and the hard mask;

removing the oxide material above the hard mask;

forming a photoresist layer to cover the second fin;

removing the hard mask on the first fin and then etching the first fin;

removing the photoresist layer and the hard mask on the second fin; and

etching the oxide material to form an oxide layer, wherein the surface of the oxide layer is uniform and even plane, and the distance between the oxide layer and top of the first fin is smaller the distance between the oxide layer and top of the second fin;

wherein the step of etching the oxide layer is performed after the step of etching the first fin.

2. The manufacturing method according to claim 1 , further comprising:

forming a gate dielectric layer on the fins; and

forming a gate electrode layer on the gate dielectric layer.

3. The manufacturing method according to claim 2 , wherein the semiconductor structure is a FINFET device.

4. The manufacturing method according to claim 1 , wherein the oxide layer has a uniform thickness between 400 Å and 600 Å.

5. The manufacturing method according to claim 1 , wherein the first fin and the second fin have different V T value.

6. The manufacturing method according to claim 1 , wherein the first fin and the second fin are doped to provide differently doped channel regions to modulate V T value.

7. The manufacturing method according to claim 1 , further comprising:

doping the fins with angled implants so as the first fin and the second fin have different doping concentration.

8. The manufacturing method according to claim 1 , wherein the distance between the oxide layer and top of the first fin is larger than 50 Å.

9. The manufacturing method according to claim 1 , wherein the distance between the oxide layer and top of the second fin is from 300 Å to 500 Å.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2014
From: WANG, JUN-JIE; TSAO, PO-CHAO; WEI, MING-TE; TZOU, SHIH-FANG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 031889/0856 →