Fin structure of semiconductor device
A fin structure of a semiconductor device, such as a fin field effect transistor (FinFET), and a method of manufacture, is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin. A dielectric material is formed in the trenches. Portions of the semiconductor material of the fin are replaced with a second semiconductor material and a third semiconductor material, the second semiconductor material having a different lattice constant than the substrate and the third semiconductor material having a different lattice constant than the second semiconductor material. Portions of the second semiconductor material are oxidized.
1. A fin field effect transistor (FinFET) comprising:
a substrate;
a fin structure extending from the substrate, the fin structure comprising a lower portion, an upper portion, and a middle portion interposed between the lower portion and the upper portion, the middle portion having a lattice constant different than lattice constants of the lower portion and the upper portion, the middle portion having oxidized portions along opposing sidewalls;
isolation regions adjacent opposing sides of the fin structure; and
a liner interposed between the isolation regions and the oxidized portions.
2. The FinFET of claim 1 , wherein the oxidized portions extend along a channel region of the fin.
3. The FinFET of claim 1 , wherein the liner comprises an oxynitride layer.
4. The FinFET of claim 1 , wherein the liner comprises an oxide layer and a nitride layer over the oxide layer.
5. The FinFET of claim 1 , wherein the liner completely separates the oxidized portions from the isolation regions.
6. The FinFET of claim 1 , wherein the oxidized portions and the liner bulge towards the isolation regions.
7. The FinFET of claim 1 , wherein the oxidized portions comprises GeOx or SiGeOx.
8. The FinFET of claim 1 , wherein the middle portion of the fin structure comprises Ge or SiGe.
9. A fin field effect transistor (FinFET) comprising:
a substrate;
a plurality of trenches in the substrate, a fin interposed between adjacent ones of the trenches, the fin comprising a first semiconductor material and a second semiconductor material on the first semiconductor material;
a first dielectric material in the trenches;
notches of a second dielectric material along sidewalls of the second semiconductor material, the second dielectric material being an oxide of the second semiconductor material; and
a dielectric liner interposed between the first dielectric material and the second dielectric material.
10. The FinFET of claim 9 , wherein the first semiconductor material has a different lattice constant than the second semiconductor material.
11. The FinFET of claim 9 , wherein the fin further comprises a third semiconductor material on the second semiconductor material, the third semiconductor material having a different lattice constant than the second semiconductor material.
12. The FinFET of claim 9 , wherein the dielectric liner completely separates the first dielectric material and the second dielectric material.
13. The FinFET of claim 9 , wherein the dielectric liner comprises an oxide layer and a nitride layer.
14. The FinFET of claim 9 , wherein the dielectric liner comprises an oxynitride.
15. A fin field effect transistor (FinFET) comprising:
a substrate;
a fin structure extending from the substrate, the fin structure comprising a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer, the second semiconductor layer interposed between the first semiconductor layer and the third semiconductor layer, the second semiconductor layer having a different lattice constant than the first semiconductor layer and the third semiconductor layer;
oxide regions along opposing sidewalls of the second semiconductor layer, the oxide regions being an oxide of a material of the second semiconductor layer;
isolation regions adjacent opposing sides of the fin structure; and
a liner interposed between the isolation regions and the oxide regions.
16. The FinFET of claim 15 , wherein the first semiconductor layer has a different lattice constant than the third semiconductor layer.
17. The FinFET of claim 15 , wherein the liner completely separates the oxide regions from the isolation regions.
18. The FinFET of claim 15 , wherein the oxide regions extend along a channel region of the fin.
19. The FinFET of claim 15 , wherein the oxide regions comprises GeOx or SiGeOx.
20. The FinFET of claim 15 , wherein a width of the oxide regions and the second semiconductor layer is greater than a width of the third semiconductor layer.