IP Library Granted Patent US 9,257,423
Granted Patent B2
US 9,257,423 · App. 14/090,673 · Granted Feb 9, 2016

Method to provide the thinnest and variable substrate thickness for reliable plastic and flexible electronic device

Inventors: Calvin Leung (Singapore, SG); Olivier Le Neel (Singapore, SG)
Assignee: STMicroelectronics Pte. Ltd.
H01L27/0629H01L21/568H01L21/76895H01L23/3135H01L23/49822H01L23/5389H01L2224/18H01L2924/0002
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Quick Facts
Patent No.
US 9,257,423
App. No.
14/090,673
Granted
Feb 9, 2016
Kind
B2
Abstract

An electronic device is formed by depositing polyimide on a glass substrate. A conductive material is deposited on the polyimide and patterned to form electrodes and signal traces. Remaining portions of the electronic device are formed on the polyimide. A second polyimide layer is then formed on the first polyimide layer. The glass substrate is then removed, exposing the electrodes and the top surface of the electronic device.

Claims (34)

1. A device comprising:

a first dielectric layer;

a second dielectric layer on the first dielectric layer, the second dielectric layer having a planar top surface;

an electronic device positioned between the first and second dielectric layers, the electronic device having a first and a second terminal;

a plurality of apertures in a top surface of the second dielectric layer;

a plurality of contact pads of a first conductive layer each in a respective one of the plurality of apertures and having respective top surfaces planar with the top surface of the second dielectric layer; and

signal lines of the first conductive layer on the first dielectric layer, the first and second terminals of the electronic device in contact with two respective signal lines.

2. The device of claim 1 wherein the electronic device includes one or more transistors.

3. The device of claim 1 comprising a capacitor positioned between the first and second dielectric layers, the capacitor including:

a first capacitor terminal of a second conductive layer on the second dielectric layer;

a third dielectric layer on the first capacitor terminal; and

a second capacitor terminal of the first conductive layer on the third dielectric layer.

4. The device of claim 3 comprising a resistor of the second conductive layer coupled between two of the signal lines.

5. The device of claim 1 wherein the second dielectric layer is less than 10 μm thick.

6. The device of claim 1 comprising a third dielectric layer on the second dielectric layer.

7. The device of claim 6 comprising wherein the first, second, and third dielectric layers have a combined thickness less than 20 μm thick.

8. The device of claim 1 wherein the first dielectric layer is polyimide.

9. The device of claim 8 wherein the second dielectric layer is polyimide.

10. The device of claim 1 wherein the first metal layer is gold.

11. The device of claim 1 wherein the electronic device is an integrated circuit die, a thin film resistor, a thin film transistor, a capacitor, a Memristor, or a battery.

12. A device comprising:

a first dielectric layer;

a second dielectric layer on the first dielectric layer, the second dielectric layer having a planar top surface;

an electronic device positioned between the first and second dielectric layers, the electronic device having a first and a second terminal;

a plurality of apertures in a top surface of the second dielectric layer; and

a plurality of contact pads of a first conductive layer each in a respective one of the plurality of apertures and having respective top surfaces planar with the top surface of the second dielectric layer, the first and second terminals of the electronic device in contact with two respective contact pads.

13. The device of claim 12 comprising signal lines of the first conductive layer on the first dielectric layer.

14. The device of claim 12 wherein the second dielectric layer is less than 10 μm thick.

15. The device of claim 12 comprising a third dielectric layer on the second dielectric layer.

16. The device of claim 15 comprising wherein the first, second and third dielectric layers have a combined thickness less than 20 μm thick.

17. The device of claim 12 wherein the first dielectric layer is polyimide.

18. The device of claim 17 wherein the second dielectric layer is polyimide.

19. The device of claim 12 wherein the first metal layer is gold.

20. The device of claim 12 wherein the electronic device is an integrated circuit die, a thin film resistor, a thin film transistor, a capacitor, a Memristor, or a battery.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2022
From: STMICROELECTRONICS PTE LTD
To: STMICROELECTRONICS INTERNATIONAL N.V.
Reel/Frame 061608/0496 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2014
From: LEUNG, CALVIN; LE NEEL, OLIVIER
To: STMICROELECTRONICS PTE. LTD.
Reel/Frame 031969/0851 →
Continuity (1)
Related Publication 20150145137A1 · May 28, 2015