Wafer dicing method for improving die packaging quality

1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits (ICs), the method comprising:

forming a mask over the semiconductor wafer covering the plurality of ICs, the plurality of ICs including metal bumps or pads with an oxidation layer;

patterning the mask with a laser scribing process to provide a patterned mask with gaps, removing non-silicon materials and exposing a silicon substrate of the semiconductor wafer between the ICs; and

plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the plurality of ICs and remove the oxidation layer from the metal bumps or pads.

2. The method of claim 1 , wherein forming the mask over the semiconductor wafer comprises depositing the mask with a thickness of 1-5 μm over the metal bumps or pads.

3. The method of claim 1 , wherein the metal bumps or pads comprise a tin alloy.

4. The method of claim 1 , further comprising:

aligning the singulated ICs with a second plurality of ICs comprising second metal bumps or pads; and

applying pressure to bond the metal bumps or pads with the second metal bumps or pads without flux.

5. The method of claim 1 , wherein the semiconductor wafer has a diameter of at least 300 mm and a thickness of 75 μm or less.

6. The method of claim 1 , wherein patterning the mask further comprises direct writing a pattern with a femtosecond laser having a wavelength less than or equal to 540 nanometers and a laser pulse width less than or equal to 500 femtoseconds.

7. The method of claim 6 , wherein plasma etching the semiconductor wafer through the gaps in the patterned mask to singulate the plurality of ICs and remove the oxidation layer from the metal bumps or pads comprises iterations of:

anisotropically etching the semiconductor wafer through the gaps in the patterned mask;

isotropically etching the anisotropically etched trench; and

polymer deposition on a surface of the semiconductor wafer and newly formed surfaces due to anisotropic and isotropic etching.

8. The method of claim 1 , wherein forming the mask further comprises depositing a water-soluble mask layer on the semiconductor wafer.

9. The method of claim 8 , wherein forming the mask further comprises depositing a multi-layered mask comprising the water-soluble mask layer as a base coat and a non-water-soluble mask layer as an overcoat on top of the base coat.

10. A method of dicing a substrate comprising a plurality of integrated circuits (ICs), the method comprising:

patterning, with a laser scribe process, a mask disposed above the substrate to form a trench exposing regions of the substrate between the ICs, wherein the mask is thicker over a dicing street than over metal bumps or pads of the plurality of ICs; and

plasma etching the substrate in the exposed regions to singulate the plurality of ICs and remove an oxidation layer from the metal bumps or pads.

11. The method of claim 10 , further comprising:

forming the mask having a thickness of 1-5 μm over the metal bumps or pads.

12. The method of claim 10 , wherein the metal bumps or pads comprise a tin alloy.

13. The method of claim 10 , further comprising:

aligning the singulated ICs with a second plurality of ICs comprising second metal bumps or pads; and

applying pressure to bond the metal bumps or pads with the second metal bumps or pads without flux.

14. The method of claim 13 , wherein plasma etching the substrate in the exposed regions to singulate the plurality of ICs and remove the oxidation layer from the metal bumps or pads comprises:

anisotropically etching the trench in the substrate, wherein anisotropic etching comprises polymer deposition and directional bombardment etch; and

isotropically etching the anisotropically etched trench.

15. The method of claim 10 , further comprising:

depositing a water-soluble mask layer over the substrate, forming the mask.

16. The method of claim 15 , wherein forming the mask further comprises depositing a multi-layered mask comprising the water-soluble mask layer as a base coat and a non-water-soluble mask layer as an overcoat on top of the base coat.

17. A system for dicing a substrate comprising a plurality of integrated circuits (ICs), the system comprising:

a deposition module to apply a mask over the substrate covering the plurality of ICs, the plurality of ICs having metal bumps or pads with an oxidation layer;

a laser scribe module to pattern the mask to form a trench exposing regions of the substrate between the ICs; and

a plasma etch module physically coupled to the laser scribe module to etch the substrate in the exposed regions to singulate the plurality of ICs and remove the oxidation layer from the metal bumps or pads.

18. The system of claim 17 , wherein the deposition module to apply the mask is to apply the mask having a thickness of 1-5 μm over the metal bumps or pads, and a second thickness over a dicing street which is greater than the thickness over the metal bumps or pads.

19. The system of claim 17 , wherein the laser scribe module comprises a femtosecond laser having a wavelength less than or equal to 540 nanometers and a pulse width of less than or equal to 500 femtoseconds.

20. The system claim 17 , wherein the plasma etch module is to perform iterations of:

anisotropically etching the substrate in the exposed regions;

isotropically etching the anisotropically etched trench; and

polymer deposition on a surface of the substrate and newly formed surfaces due to anisotropic and isotropic etching.