Method for producing microbumps on a semiconductor component
The disclosed technology relates to pillar-type microbumps formed on a semiconductor component, such as an integrated circuit chip or an interposer substrate, and a method of forming the pillar-type microbumps. In one aspect, a method of forming the pillar-type microbump on a semiconductor component includes providing the semiconductor component, where the semiconductor component has an upper metallization layer, and the metallization layer has a contact area. The method additionally includes forming a passivation layer over the metallization layer. The method additionally includes forming a plurality of openings through the passivation layer such that the contact area is exposed at a bottom of the openings. The method further includes forming the microbump over the contact area, where the microbump forms an electrical connection with the contact area through the openings.
1. A semiconductor package, comprising:
a first component;
a second component; and
a plurality of pillar-type microbumps forming an electrical connection between the first and second components,
wherein at least one of the plurality of microbumps contacts at least one of the first and second components through a plurality of contact openings formed through a passivation layer.
2. The semiconductor package of claim 1 , wherein the openings have slanted side walls.
3. The semiconductor package of claim 2 , wherein the slanted side walls and a plane of the passivation layer forms an angle between about 50° and about 85°.
4. The semiconductor package of claim 1 , wherein the openings are arranged in a regularly repeating pattern.
5. The semiconductor package of claim 1 , wherein each of the maximum diameter of the openings and the maximum distance between two neighboring openings is between about 0.5 μm and about 4 μm.
6. The semiconductor package of claim 1 , further comprising a contact pad covering the plurality of contact openings, wherein one of the microbumps are formed on the contact pad.
7. The semiconductor package of claim 1 , wherein one of the first and second components is an integrated circuit chip.